Analytical modeling for multi-transaction bus on distributed systems

Authors:
Jih-Ching Chiu;Kai-Ming Yang;Chen-Ang Wong
Affiliations:
Department of Electrical Engineering, National Sun Yat-Sen University, Kaohsiung, Taiwan, R.O.C.;Department of Electrical Engineering, National Sun Yat-Sen University, Kaohsiung, Taiwan, R.O.C.;Department of Electrical Engineering, National Sun Yat-Sen University, Kaohsiung, Taiwan, R.O.C.
Venue:
ICA3PP'12 Proceedings of the 12th international conference on Algorithms and Architectures for Parallel Processing - Volume Part II
Year:
2012

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Abstract

Network-on-Chip (NoC) has been proposed to perform high performance and scalability in System-on-Chip (SoC) design. Interconnection modeling was widely used to evaluate performance, especially for large-scale NoCs. In this paper, the router modeling for multi-transaction bus architecture on distributed system with bufferless microarchitectures was presented to analyze and evaluate the performance and model the success rate of each node respectively. It will facilitate the analysis of impact for different priorities. The accuracy of our approach and its practical use is illustrated through extensive simulation results.