Lowering power consumption in clock by using globally asynchronous locally synchronous design style
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Modular Asynchronous Arbiter Insensitive to Metastability
IEEE Transactions on Computers
The design of easily scalable bus arbiters with different dynamic priority assignment schemes
ASILOMAR '95 Proceedings of the 29th Asilomar Conference on Signals, Systems and Computers (2-Volume Set)
Delay Insensitive System-on-Chip Interconnect using 1-of-4 Data Encoding
ASYNC '01 Proceedings of the 7th International Symposium on Asynchronous Circuits and Systems
Point to Point GALS Interconnect
ASYNC '02 Proceedings of the 8th International Symposium on Asynchronus Circuits and Systems
TITAC-2: an asynchronous 32-bit microprocessor based on scalable-delay-insensitive model
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
High-Level Modeling and Design of Asynchronous Arbiters for On-Chip Communication Systems
Proceedings of the conference on Design, automation and test in Europe
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This paper presents a scalable and partitionable asynchronous bus arbiter for use with chip multiprocessors and its corresponding pre-layout simulation results using VHDL. The arbiter exploits the advantage of a concurrency control instruction (Brk) provided by the micro-threaded microprocessor model to set the priority processor and move the circulated arbitration token to the most likely processor to issue the create instruction. This mechanism provides latency hiding during token circulation by decoupling the micro-threaded processor from the ring's timing. The arbiter provides a very simple arbitration mechanism and can be used for chip multiprocessor arbitration purposes.