High-Level Modeling and Design of Asynchronous Arbiters for On-Chip Communication Systems

Authors:
J. Rigaud;L. Fesquet;M. Renaudin;J. Quartana
Affiliations:
TIMA Laboratory, 46 ay. Felix Viallet 38031 Grenoble, France;TIMA Laboratory, 46 ay. Felix Viallet 38031 Grenoble, France;TIMA Laboratory, 46 ay. Felix Viallet 38031 Grenoble, France;STMicroelectronics
Venue:
Proceedings of the conference on Design, automation and test in Europe
Year:
2002

Citing 0
Cited 3

Asynchronous arbiter for micro-threaded chip multiprocessors

Journal of Systems Architecture: the EUROMICRO Journal
A priority assignment strategy of processing elements over an on-chip bus

Proceedings of the 2007 ACM symposium on Applied computing
Scalable and partitionable asynchronous arbiter for micro-threaded chip multiprocessors

ARCS'06 Proceedings of the 19th international conference on Architecture of Computing Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract