Sizing of clock distribution networks for high performance CPU chips
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Lowering power consumption in clock by using globally asynchronous locally synchronous design style
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A resonant clock generator for single-phase adiabatic systems
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
High-Speed Digital System Design: A Handbook of Interconnect Theory and Design Practices
High-Speed Digital System Design: A Handbook of Interconnect Theory and Design Practices
Low-power clock distribution using multiple voltages and reduced swings
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On the Micro-Architectural Impact of Clock Distribution Using Multiple PLLs
ICCD '01 Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors
Impact of Technology Scaling in the Clock System Power
ISVLSI '02 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
Reducing clock skew variability via cross links
Proceedings of the 41st annual Design Automation Conference
Modeling, optimization and control of rotary traveling-wave oscillator
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Custom topology rotary clock router with tree subnetworks
ACM Transactions on Design Automation of Electronic Systems (TODAES)
ZeROA: zero clock skew rotary oscillatory array
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Rotary clock is a recently proposed clock distribution technique based on wave propagation in transmission lines. In this paper, we investigate the problem of power minimization of rotary clock designs. Specifically, we have developed a software tool based on the method of partial element equivalent circuit that is capable of extracting the SPICE netlist from the layout specification of a rotary clock design. Using our tool, we have performed extensive analysis that links various design parameters of a rotary clock design to its oscillation frequency and power dissipation. Based on the results of our analysis, we then propose a power minimization algorithm. Our algorithm derives a rotary clock structure that dissipates the minimal power while satisfying the clock dimension requirement and oscillating at the target frequency with the given clock load. Experimental results have demonstrated that, for target operating frequencies ranging from 0.5 to 5 GHz, rotary clock designs can achieve power savings of up to 80% in comparison with conventional clock tree implementations.