Design and optimization of LC oscillators
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Power Analysis of Rotary Clock
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Low-power rotary clock array design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design of Analog CMOS Integrated Circuits
Design of Analog CMOS Integrated Circuits
A clock power model to evaluate impact of architectural and technology optimizations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
PEEC based parasitic modeling for power analysis on custom rotary rings
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
High-performance, low-power resonant clocking
Proceedings of the International Conference on Computer-Aided Design
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Rotary traveling-wave oscillator (RTWO) is a recently proposed transmission-line approach for multi-gigahertz rate clock generation. RTWO has the characteristics of both conventional LC tank oscillator and ring oscillator. Thus, it is difficult to be analyzed by a general-purpose method. This paper presents a systematic and efficient method for RTWO modeling and optimization. Equations for frequency, power dissipation, die area, loop gain and phase noise are formulated in posynomial forms. The resulting optimization problem is relaxed to be a Geometric Programming (GP) and can be efficiently solved with a convex optimization solver. A novel scheme to control the rotation direction is also suggested for skew control. Experimental results show that our method can rapidly compute the globally optimal trade-off and reduce the power by up to 85% for a 11.8 GHz RTWO design. Compared to a recently reported low-power methodology, the proposed design scheme can save about 50% of die area and achieve lower power dissipation as well as faster rise/fall time.