Power-aware clock tree planning
Proceedings of the 2004 international symposium on Physical design
A low-power reduced swing global clocking methodology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power Analysis of Rotary Clock
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Low-power rotary clock array design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Rapid design space exploration using legacy design data and technology scaling trend
Integration, the VLSI Journal
Effective and efficient approach for power reduction by using multi-bit flip-flops
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Routability-constrained multi-bit flip-flop construction for clock power reduction
Integration, the VLSI Journal
| Hi-index | 0.00 |
The clock distribution and generation circuitry is known to consume more than a quarter of the power budget of existing microprocessors. A previously derived clock energy model is briefly reviewed while a comprehensive framework for the estimation of system-wide (chip level) and clock sub-system power as function of technology scaling is presented. This framework is used to study and quantify the impact that various intensifying concerns associated with scaling (i.e., increased leakage currents, increased interwire capacitance) will have on clock energy and their relative impact on the overall system energy. The results obtained indicate that clock power will remain a significant contributor to the total chip power, as long as techniques are used to limit leakage power consumption.