Low Power Digital CMOS Design
Flip-Flop and Repeater Insertion for Early Interconnect Planning
Proceedings of the conference on Design, automation and test in Europe
Impact of Technology Scaling in the Clock System Power
ISVLSI '02 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
Spec Based Flip-Flop And Buffer Insertion
ICCD '03 Proceedings of the 21st International Conference on Computer Design
Leveraging Delay Slack in Flip-Flop and Buffer Insertion for Power Reduction
ISQED '04 Proceedings of the 5th International Symposium on Quality Electronic Design
Timing-constrained congestion-driven global routing
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Prediction and reduction of routing congestion
Proceedings of the 2006 international symposium on Physical design
Fast and accurate routing demand estimation for efficient routability-driven placement
Proceedings of the conference on Design, automation and test in Europe
Automatic register banking for low-power clock trees
ISQED '09 Proceedings of the 2009 10th International Symposium on Quality of Electronic Design
Post-placement power optimization with multi-bit flip-flops
Proceedings of the International Conference on Computer-Aided Design
In-placement clock-tree aware multi-bit flip-flop generation for power optimization
Proceedings of the International Conference on Computer-Aided Design
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Reducing the power consumption of a clock network is always one of critical issues in designing a high performance design. The concept of multi-bit flip-flop construction has been introduced by recent studies and shown the benefits of reducing clock power and decreasing the total flip-flop area in a synchronous design. However, all the works are not considering the routability issue which caused by merging multiple 1-bit flip-flops into multi-bit flip-flops. In this paper, given a set of 1-bit flip-flops with the input and output timing constraints, the area constraint inside any partitioned bin and the capacity constraint on any bin edge in a placement plane, an efficient routability-constrained approach is proposed to merge 1-bit flip-flops into some multi-bit flip-flops for clock power reduction. The experimental results show that our proposed approach reduces 37.4% of the flip-flop area to maintain the synchronous design and saves 24.82% of the clock power for five examples in reasonable CPU time on the average.