Power-driven flip-flop merging and relocation
Proceedings of the 2011 international symposium on Physical design
INTEGRA: fast multi-bit flip-flop clustering for clock power saving based on interval graphs
Proceedings of the 2011 international symposium on Physical design
Implementation of pulsed-latch and pulsed-register circuits to minimize clocking power
Proceedings of the International Conference on Computer-Aided Design
Post-placement power optimization with multi-bit flip-flops
Proceedings of the International Conference on Computer-Aided Design
Effective and efficient approach for power reduction by using multi-bit flip-flops
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Agglomerative-based flip-flop merging with signal wirelength optimization
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
In-placement clock-tree aware multi-bit flip-flop generation for power optimization
Proceedings of the International Conference on Computer-Aided Design
Clock power minimization using structured latch templates and decision tree induction
Proceedings of the International Conference on Computer-Aided Design
Routability-constrained multi-bit flip-flop construction for clock power reduction
Integration, the VLSI Journal
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We present an automatic register placement technique that enables the synthesis of low-power clock trees for low-power ICs. On 7 industrial designs, comparing to (1) a commercial base flow and (2) the power-aware placement technique in, the technique respectively reduced clock-tree power by 19.0% and 14.9%, total power by 15.3% and 5.2% and WNS under on-chip variation (plusmn10%) by 1.8% and 1.5% on average.