Useful-skew clock routing with gate sizing for low power design
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Buffered Clock Tree for High Quality IC Design
ISQED '04 Proceedings of the 5th International Symposium on Quality Electronic Design
Proceedings of the 42nd annual Design Automation Conference
Clock network minimization methodology based on incremental placement
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Computational geometry based placement migration
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Non-wrapping order crossover: an order preserving crossover operator that respects absolute position
Proceedings of the 8th annual conference on Genetic and evolutionary computation
Working Set Selection Using Second Order Information for Training Support Vector Machines
The Journal of Machine Learning Research
FastPlace 3.0: A Fast Multilevel Quadratic Placement Algorithm with Placement Congestion Control
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
A Survey on Training Algorithms for Support Vector Machine Classifiers
NCM '08 Proceedings of the 2008 Fourth International Conference on Networked Computing and Advanced Information Management - Volume 01
Proceedings of the 2009 international symposium on Physical design
Automatic register banking for low-power clock trees
ISQED '09 Proceedings of the 2009 10th International Symposium on Quality of Electronic Design
ISPD 2010 high performance clock network synthesis contest: benchmark suite and results
Proceedings of the 19th international symposium on Physical design
IBM POWER7 processor circuit design
IBM Journal of Research and Development
Myth busters: microprocessor clocking is from Mars, ASICs clocking is from Venus
Proceedings of the International Conference on Computer-Aided Design
Local clock skew minimization using blockage-aware mixed tree-mesh clock network
Proceedings of the International Conference on Computer-Aided Design
Time complexity of decision trees
Transactions on Rough Sets III
Proceedings of the 49th Annual Design Automation Conference
RUMBLE: An Incremental Timing-Driven Physical-Synthesis Optimization Algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A survey of cost-sensitive decision tree induction algorithms
ACM Computing Surveys (CSUR)
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This work proposes a novel latch placement methodology by computing optimized placement templates with significantly lower local clock tree capacitance at a one-time cost per standard cell library. By directly minimizing local clock tree capacitance, overall chip power is reduced. The proposed methodology first generates optimized placement solutions for a wide range of input configurations. Then, a redundancy removal approach using set-theoretic annotation is proposed demonstrating it is possible to remove over 99% of the templates with no information loss. Finally, a decision tree induction algorithm with novel impurity metric enables extremely fast template selection during the clock optimization stage of a modern physical design flow. The proposed approach reduces the local clock tree capacitance by 20-30% on average roughly equating to between a 1 and 4 watt reduction in total dynamic power on a 100-watt 22-nm microprocessor. Additionally, because of a priori generation, template selection during physical design is extremely fast.