Physical Synthesis with Clock-Network Optimization for Large Systems on Chips

Authors:
David Papa;Charles Alpert;Cliff Sze;Zhuo Li;Natarajan Viswanathan;Gi-Joon Nam;Igor Markov
Affiliations:
Broadway Technology;IBM;IBM Austin Research Laboratory;IBM Austin Research Laboratory;IBM Austin Research Laboratory;IBM Austin Research Laboratory;University of Michigan, Ann Arbor
Venue:
IEEE Micro
Year:
2011

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Abstract

In traditional physical-synthesis methodologies, the placement of flip-flops and latches is problematic, especially for large systems on chips. A next-generation electronic-design-automation methodology improves timing closure through clock-network synthesis and placement of flip-flops and latches to avoid timing disruptions or immediately recover from them. When evaluated on large CPU designs, the methodology saw double-digit improvements in timing, wirelength, and area versus current technology.