Dealing with inductance in high-speed chip design
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Clocking design automation in Intel's core i7 and future designs
Proceedings of the International Conference on Computer-Aided Design
Revisiting automated physical synthesis of high-performance clock networks
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Clock power minimization using structured latch templates and decision tree induction
Proceedings of the International Conference on Computer-Aided Design
| Hi-index | 0.00 |
This paper compares and contrasts two common clock distribution styles: clock grids, the preferred microprocessor distribution style, and clock trees, the preferred ASICs distribution style. After a high level description of the routing methodologies for clock grids and clock trees, a case study is presented to compare the performance and cost trade-off of grids and trees. Our results show that clock grids consume more power and wiring resources but only to achieve aggressive clock targets. In this example a clock tree style uses 28% less wiring than a full clock grid style but suffers 12 ps more skew. However, compared to a sparse grid style, a clock tree solution uses only 4% less wiring and suffers 9.6 ps higher skew. The key message is that the cost in extra wiring and power consumption across different clock distribution styles is mainly driven by performance targets as opposed to being fundamentally dictated by the grid vs. tree decision.