Buffer insertion and sizing under process variations for low power clock distribution
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
On the bounded-skew clock and Steiner routing problems
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Timing-driven placement for FPGAs
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
Computing Minimum-Weight Perfect Matchings
INFORMS Journal on Computing
Clock-tree power optimization based on RTL clock-gating
Proceedings of the 40th annual Design Automation Conference
Buffer sizing for clock power minimization subject to general skew constraints
Proceedings of the 41st annual Design Automation Conference
Navigating registers in placement for clock network minimization
Proceedings of the 42nd annual Design Automation Conference
Proceedings of the 42nd annual Design Automation Conference
Automatic register banking for low-power clock trees
ISQED '09 Proceedings of the 2009 10th International Symposium on Quality of Electronic Design
Pulsed-latch aware placement for timing-integrity optimization
Proceedings of the 47th Design Automation Conference
Implementation and extensibility of an analytic placer
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Post-Placement Power Optimization With Multi-Bit Flip-Flops
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
INTEGRA: Fast Multibit Flip-Flop Clustering for Clock Power Saving
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
ISPD11: Power-Driven Flip-Flop Merging and Relocation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
FF-bond: multi-bit flip-flop bonding at placement
Proceedings of the 2013 ACM international symposium on International symposium on physical design
Effective and efficient approach for power reduction by using multi-bit flip-flops
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Agglomerative-based flip-flop merging with signal wirelength optimization
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Routability-constrained multi-bit flip-flop construction for clock power reduction
Integration, the VLSI Journal
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Utilizing multi-bit flip-flops (MBFFs) is one of the most effective power optimization techniques in modern nanometer integrated circuit (IC) design. Most of the previous work apply MBFFs without doing placement refinement of combinational logic cells. Such problem formulation may result in less power reduction due to tight timing constraints with fixed combinational logic cells. This paper introduces a novel placement flow with clock-tree aware flip-flop merging and MBFF generation, and proposes the corresponding algorithms to simultaneously minimize flip-flop power and clock latency when applying MBFFs during placement. Experimental results based on the IWLS-2005 benchmark show that our approach is very effective in not only flip-flop power but also clock latency minimization without degrading circuit performance. To our best knowledge, this is also the first work in the literature which considers clock trees during flip-flop merging and MBFF generation.