Algorithm 457: finding all cliques of an undirected graph
Communications of the ACM
Navigating registers in placement for clock network minimization
Proceedings of the 42nd annual Design Automation Conference
Proceedings of the 42nd annual Design Automation Conference
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Automatic register banking for low-power clock trees
ISQED '09 Proceedings of the 2009 10th International Symposium on Quality of Electronic Design
Power-driven flip-flop merging and relocation
Proceedings of the 2011 international symposium on Physical design
INTEGRA: fast multi-bit flip-flop clustering for clock power saving based on interval graphs
Proceedings of the 2011 international symposium on Physical design
Obstacle-aware clock-tree shaping during placement
Proceedings of the 2011 international symposium on Physical design
Algorithmic tuning of clock trees and derived non-tree structures
Proceedings of the International Conference on Computer-Aided Design
Implementation of pulsed-latch and pulsed-register circuits to minimize clocking power
Proceedings of the International Conference on Computer-Aided Design
Progress and challenges in VLSI placement research
Proceedings of the International Conference on Computer-Aided Design
Proceedings of the International Conference on Computer-Aided Design
FF-bond: multi-bit flip-flop bonding at placement
Proceedings of the 2013 ACM international symposium on International symposium on physical design
Slack budgeting and slack to length converting for multi-bit flip-flop merging
Proceedings of the Conference on Design, Automation and Test in Europe
Effective and efficient approach for power reduction by using multi-bit flip-flops
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Agglomerative-based flip-flop merging with signal wirelength optimization
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Routability-constrained multi-bit flip-flop construction for clock power reduction
Integration, the VLSI Journal
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Optimization for power is always one of the most important design objectives in modern nanometer IC design. Recent studies have shown the effectiveness of applying multi-bit flip-flops to save the power consumption of the clock network. However, all the previous works applied multi-bit flip-flops at earlier design stages, which could be very difficult to carry out the trade-off among power, timing, and other design objectives. This paper presents a novel power optimization method by incrementally applying more multi-bit flip-flops at the post-placement stage to gain more clock power saving while considering the placement density and timing slack constraints, and simultaneously minimizing interconnecting wirelength. Experimental results based on the industry benchmark circuits show that our approach is very effective and efficient, which can be seamlessly integrated in modern design flow.