A fast physical constraint generator for timing driven layout
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Iterative and adaptive slack allocation for performance-driven layout and FPGA routing
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
On gate level power optimization using dual-supply voltages
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Optimal integer delay budgeting on directed acyclic graphs
Proceedings of the 40th annual Design Automation Conference
Potential Slack Budgeting with Clock Skew Optimization
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
Coarse-grain MTCMOS sleep transistor sizing using delay budgeting
Proceedings of the conference on Design, automation and test in Europe
Simultaneous slack budgeting and retiming for synchronous circuits optimization
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Bounded potential slack: enabling time budgeting for dual-Vt allocation of hierarchical design
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Power-driven flip-flop merging and relocation
Proceedings of the 2011 international symposium on Physical design
INTEGRA: fast multi-bit flip-flop clustering for clock power saving based on interval graphs
Proceedings of the 2011 international symposium on Physical design
Post-placement power optimization with multi-bit flip-flops
Proceedings of the International Conference on Computer-Aided Design
Generation of performance constraints for layout
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A delay budgeting algorithm ensuring maximum flexibility in placement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Unified Theory of Timing Budget Management
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
FLUTE: Fast Lookup Table Based Rectilinear Steiner Minimal Tree Algorithm for VLSI Design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Post-Placement Power Optimization With Multi-Bit Flip-Flops
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
ISPD11: Power-Driven Flip-Flop Merging and Relocation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Agglomerative-based flip-flop merging with signal wirelength optimization
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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In this paper we propose a flexible slack budgeting approach for post-placement multi-bit flip-flop (MBFF) merging. Our approach considers existing wiring topology and flip-flop delay changes for achieving more accurate slack budgeting. Besides, we propose a slack-to-length converting approach to translating timing slack into equivalent wire length for simplifying a merging process. We also develop a merging method to evaluate our slack budgeting approach. Our slack budgeting and MBFF merging programs are fully integrated into an industrial design flow. Experimental results show that our approach on average achieves 3.4% area saving, 50% clock tree power saving, and 5.3% total power saving.