The coming of age of physical synthesis
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
The coming of age of (academic) global routing
Proceedings of the 2008 international symposium on Physical design
Fast buffering for optimizing worst slack and resource consumption in repeater trees
Proceedings of the 2009 international symposium on Physical design
GRIP: scalable 3D global routing using integer programming
Proceedings of the 46th Annual Design Automation Conference
CRISP: congestion reduction by iterated spreading during placement
Proceedings of the 2009 International Conference on Computer-Aided Design
Proceedings of the 2009 International Conference on Computer-Aided Design
A multilevel congestion-based global router
VLSI Design
FOARS: FLUTE based obstacle-avoiding rectilinear steiner tree construction
Proceedings of the 19th international symposium on Physical design
A parallel integer programming approach to global routing
Proceedings of the 47th Design Automation Conference
NTHU-route 2.0: a robust global router for modern designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
RegularRoute: an efficient detailed router with regular routing patterns
Proceedings of the 2011 international symposium on Physical design
An enhanced global router with consideration of general layer directives
Proceedings of the 2011 international symposium on Physical design
Routability-driven analytical placement for mixed-size circuit designs
Proceedings of the International Conference on Computer-Aided Design
MGR: multi-level global router
Proceedings of the International Conference on Computer-Aided Design
Exploring high throughput computing paradigm for global routing
Proceedings of the International Conference on Computer-Aided Design
GLADE: a modern global router considering layer directives
Proceedings of the International Conference on Computer-Aided Design
Routability-driven placement algorithm for analog integrated circuits
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
Algorithms and data structures for fast and good VLSI routing
Proceedings of the 49th Annual Design Automation Conference
Proceedings of the 49th Annual Design Automation Conference
Non-uniform multilevel analog routing with matching constraints
Proceedings of the 49th Annual Design Automation Conference
GLARE: global and local wiring aware routability evaluation
Proceedings of the 49th Annual Design Automation Conference
Timing ECO optimization using metal-configurable gate-array spare cells
Proceedings of the 49th Annual Design Automation Conference
A methodology for the early exploration of design rules for multiple-patterning technologies
Proceedings of the International Conference on Computer-Aided Design
Proceedings of the International Conference on Computer-Aided Design
BonnRoute: Algorithms and data structures for fast and good VLSI routing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Slack budgeting and slack to length converting for multi-bit flip-flop merging
Proceedings of the Conference on Design, Automation and Test in Europe
Routing congestion estimation with real design constraints
Proceedings of the 50th Annual Design Automation Conference
Routability optimization for crossbar-switch structured ASIC design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A fast algorithm for rectilinear steiner trees with length restrictions on obstacles
Proceedings of the 2014 on International symposium on physical design
Placement-driven partitioning for congestion mitigation in monolithic 3D IC designs
Proceedings of the 2014 on International symposium on physical design
Proceedings of the 2014 on International symposium on physical design
Techniques for scalable and effective routability evaluation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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In this paper, we present a very fast and accurate rectilinear Steiner minimal tree (RSMT) algorithm called fast lookup table estimation (FLUTE). FLUTE is based on a precomputed lookup table to make RSMT construction very fast and very accurate for low-degreeThe degree of a net is the number of pins in the net. nets. For high-degree nets, a net-breaking technique is proposed to reduce the net size until the table can be used. A scheme is also presented to allow users to control the tradeoff between accuracy and runtime. FLUTE is optimal for low-degree nets (up to degree 9 in our current implementation) and is still very accurate for nets up to degree 100. Therefore, it is particularly suitable for very large scale integration applications in which most nets have a degree of 30 or less. We show experimentally that, over 18 industrial circuits in the ISPD98 benchmark suite, FLUTE with default accuracy is more accurate than the Batched 1-Steiner heuristic and is almost as fast as a very efficient implementation of Prim's rectilinear minimum spanning tree algorithm.