An investigation of machine learning based prediction systems
Journal of Systems and Software - Special issue on empirical studies of software development and evolution
Refined single trunk tree: a rectilinear steiner tree generator for interconnect prediction
SLIP '02 Proceedings of the 2002 international workshop on System-level interconnect prediction
Accurate pseudo-constructive wirelength and congestion estimation
Proceedings of the 2003 international workshop on System-level interconnect prediction
Probabilistic congestion prediction
Proceedings of the 2004 international symposium on Physical design
Pre-layout wire length and congestion estimation
Proceedings of the 41st annual Design Automation Conference
Probabilistic Congestion Prediction with Partial Blockages
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
Simultaneous layout migration and decomposition for double patterning technology
Proceedings of the 2009 International Conference on Computer-Aided Design
A framework for early and systematic evaluation of design rules
Proceedings of the 2009 International Conference on Computer-Aided Design
A framework for double patterning-enabled design
Proceedings of the International Conference on Computer-Aided Design
WISDOM: wire spreading enhanced decomposition of masks in double patterning lithography
Proceedings of the International Conference on Computer-Aided Design
Native-conflict-aware wire perturbation for double patterning technology
Proceedings of the International Conference on Computer-Aided Design
Estimating routing congestion using probabilistic analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A predictive distributed congestion metric with application to technology mapping
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
FLUTE: Fast Lookup Table Based Rectilinear Steiner Minimal Tree Algorithm for VLSI Design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Role of design in multiple patterning: technology development, design enablement and process control
Proceedings of the Conference on Design, Automation and Test in Europe
| Hi-index | 0.00 |
Double/Multiple-patterning (DP/MP) lithography in a multiple litho-etch steps process is a favorable solution for technology scaling to the 20nm node and below. Mask-assignment conflicts represent the biggest challenge for MP and limiting them through design rules is crucial for the adoption of MP technology. In this paper, we offer a methodology for the early evaluation and exploration of layout and MP rules intended for speeding up the rules-development cycle. Using a novel wiring-estimation method, we create layout estimates with fine-grained congestion prediction. MP-conflicts are then predicted using a machine-learning approach. In this work, we demonstrate the use of the method for double-patterning lithography in litho-etch-litho-etch process; the methodology is more general, however, and can be applied for other multiple-patterning technologies including tripe/multiple-patterning with multiple litho-etch steps, self-aligned double patterning (SADP), and directed self-assembly. Results of testing the methodology on standard-cell layouts show an 81% accuracy in DP-conflicts prediction. The methodology was then used to explore DP and layout rules and investigate their effects on DP-compatibility and layout area. The methodology allows for rules optimization; for example, pushing the minimum tip-to-side same-color spacing rule value from 1.7x to 1.5x the minimum side-to-side spacing design rule (i.e., from 110nm down to 90nm) would more than double the number of DP-compatible cells in the library.