Refined single trunk tree: a rectilinear steiner tree generator for interconnect prediction

Authors:
Hongyu Chen;Changge Qiao;Feng Zhou;Chung-Kuan Cheng
Affiliations:
University of California, San Diego, La Jolla, CA;Synopsys, Inc., Mountain View, CA;University of California, San Diego, La Jolla, CA;University of California, San Diego, La Jolla, CA
Venue:
SLIP '02 Proceedings of the 2002 international workshop on System-level interconnect prediction
Year:
2002

Citing 4
Cited 10

Computational geometry: an introduction

Computational geometry: an introduction
A wire length estimation technique utilizing neighborhood density equations

DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
On wirelength estimations for row-based placement

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Prim-Dijkstra tradeoffs for improved performance-driven routing tree design

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Benchmarking for large-scale placement and beyond

Proceedings of the 2003 international symposium on Physical design
Fast and accurate rectilinear steiner minimal tree algorithm for VLSI design

Proceedings of the 2005 international symposium on Physical design
FLUTE: fast lookup table based wirelength estimation technique

Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Improved timing closure by early buffer planning in floor-placement design flow

Proceedings of the 17th ACM Great Lakes symposium on VLSI
TROY: track router with yield-driven wire planning

Proceedings of the 44th annual Design Automation Conference
Using metro-on-chip in physical design flow for congestion and routability improvement

Microelectronics Journal
An efficient rectilinear Steiner tree algorithm with obstacles

CSECS'06 Proceedings of the 5th WSEAS International Conference on Circuits, Systems, Electronics, Control & Signal Processing
On improving optimization effectiveness in interconnect-driven physical synthesis

Proceedings of the 2009 international symposium on Physical design
RegularRoute: an efficient detailed router with regular routing patterns

Proceedings of the 2011 international symposium on Physical design
A methodology for the early exploration of design rules for multiple-patterning technologies

Proceedings of the International Conference on Computer-Aided Design

Quantified Score

Hi-index	0.00

Visualization

Abstract

We devised an efficient and accurate estimation of the rectilinear Steiner minimal tree (SMT), which is an essential building block for on-line and posteriori interconnect prediction. We proposed a new rectilinear Steiner tree generator, Refined Single Trunk Tree (RST-T). Compared with traditional minimal spanning tree based Steiner tree heuristics, RST-T has several advantages. 1. The algorithm runs very fast. Experiments show that RST-T algorithm runs 50 times faster than Prim's minimum spanning tree algorithm for 10-pin nets. 2. The RST-T provides excellent wire length estimation of the optimal solutions. For the nets of no more than 10 pins, the average wire length of RST-T is within 6 percent of the optimal solutions. Actually, for the nets with five or less pins, the wire length of RST-T is optimal. 3. The topology of RST-T remains stable when pin locations deviate. Experiments show that the topologies of routing trees produced by the proposed algorithm is much more stable than the minimum spanning tree and iterative 1-Steiner heuristics.