R-trees: a dynamic index structure for spatial searching
SIGMOD '84 Proceedings of the 1984 ACM SIGMOD international conference on Management of data
Structured ASIC, evolution or revolution?
Proceedings of the 2004 international symposium on Physical design
Engineering change using spare cells with constant insertion
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
A metal-only-ECO solver for input-slew and output-loading violations
Proceedings of the 2009 international symposium on Physical design
New spare cell design for IR drop minimization in Engineering Change Order
Proceedings of the 46th Annual Design Automation Conference
Matching-based minimum-cost spare cell selection for design changes
Proceedings of the 46th Annual Design Automation Conference
ECO timing optimization using spare cells and technology remapping
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
TRECO: dynamic technology remapping for timing engineering change orders
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Simultaneous functional and timing ECO
Proceedings of the 48th Design Automation Conference
Routability-driven analytical placement for mixed-size circuit designs
Proceedings of the International Conference on Computer-Aided Design
Timing ECO optimization via Bézier curve smoothing and fixability identification
Proceedings of the International Conference on Computer-Aided Design
Redundant-wires-aware ECO timing and mask cost optimization
Proceedings of the International Conference on Computer-Aided Design
FLUTE: Fast Lookup Table Based Rectilinear Steiner Minimal Tree Algorithm for VLSI Design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Due to the rapidly increasing design complexity in modern IC designs, metal-only engineering change order (ECO) becomes inevitable to achieve design closure with a low respin cost. Traditionally, preplaced redundant standard cells are regarded as spare cells. However, these cells are limited by predefined functionalities and locations, and they always consume leakage power despite their inputs are tied off. To overcome the inflexibility and power overhead, a new type of spare cells, metal-configurable gate-array spare cells, are considered. Therefore, in this paper, we address a new ECO problem: Timing ECO optimization using metal-configurable gate-array spare cells. We first study the properties for this new ECO problem, propose a new metric, aliveness, to model the capability of a spare gate array, and then develop a timing ECO optimization framework based on aliveness, routability, and timing satisfaction. Experimental results show that our approach delivers superior efficiency and effectiveness.