Routability driven white space allocation for fixed-die standard-cell placement
Proceedings of the 2002 international symposium on Physical design
Digital Image Processing
Multilevel optimization for large-scale circuit placement
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2004 international symposium on Physical design
Multilevel generalized force-directed method for circuit placement
Proceedings of the 2005 international symposium on Physical design
Routability-driven placement and white space allocation
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Fast and accurate routing demand estimation for efficient routability-driven placement
Proceedings of the conference on Design, automation and test in Europe
IPR: an integrated placement and routing algorithm
Proceedings of the 44th annual Design Automation Conference
FastRoute 2.0: A High-quality and Efficient Global Router
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Proceedings of the 45th annual Design Automation Conference
Guiding global placement with wire density
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
CROP: fast and effective congestion refinement of placement
Proceedings of the 2009 International Conference on Computer-Aided Design
GRPlacer: improving routability and wire-length of global routing with circuit replacement
Proceedings of the 2009 International Conference on Computer-Aided Design
CRISP: congestion reduction by iterated spreading during placement
Proceedings of the 2009 International Conference on Computer-Aided Design
The ISPD-2011 routability-driven placement contest and benchmark suite
Proceedings of the 2011 international symposium on Physical design
Seeing the Forest and the Trees: Steiner Wirelength Optimization in Placement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
FLUTE: Fast Lookup Table Based Rectilinear Steiner Minimal Tree Algorithm for VLSI Design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
BonnPlace: Placement of Leading-Edge Chips by Advanced Combinatorial Algorithms
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
MAPLE: multilevel adaptive placement for mixed-size designs
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
Structure-aware placement for datapath-intensive circuit designs
Proceedings of the 49th Annual Design Automation Conference
Timing ECO optimization using metal-configurable gate-array spare cells
Proceedings of the 49th Annual Design Automation Conference
Progress and challenges in VLSI placement research
Proceedings of the International Conference on Computer-Aided Design
Proceedings of the International Conference on Computer-Aided Design
A fast maze-free routing congestion estimator with hybrid unilateral monotonic routing
Proceedings of the International Conference on Computer-Aided Design
Planning for local net congestion in global routing
Proceedings of the 2013 ACM international symposium on International symposium on physical design
SRP: simultaneous routing and placement for congestion refinement
Proceedings of the 2013 ACM international symposium on International symposium on physical design
Case study for placement solutions in ispd11 and dac12 routability-driven placement contests
Proceedings of the 2013 ACM international symposium on International symposium on physical design
LASER: layout-aware analog synthesis environment on laker
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
Sub-quadratic objectives in quadratic placement
Proceedings of the Conference on Design, Automation and Test in Europe
Taming the complexity of coordinated place and route
Proceedings of the 50th Annual Design Automation Conference
Routability-driven placement for hierarchical mixed-size circuit designs
Proceedings of the 50th Annual Design Automation Conference
Ripple 2.0: high quality routability-driven placement via global router integration
Proceedings of the 50th Annual Design Automation Conference
Optimization of placement solutions for routability
Proceedings of the 50th Annual Design Automation Conference
A study on unroutable placement recognition
Proceedings of the 2014 on International symposium on physical design
MIP-based detailed placer for mixed-size circuits
Proceedings of the 2014 on International symposium on physical design
ISPD 2014 benchmarks with sub-45nm technology rules for detailed-routing-driven placement
Proceedings of the 2014 on International symposium on physical design
Techniques for scalable and effective routability evaluation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Due to the significant mismatch between existing wirelength models and the congestion objective in placement, considering routability during placement is particularly significant for modern circuit designs. In this paper, a novel routability-driven analytical placement algorithm for large-scale mixed-size circuit designs is proposed. Unlike most existing works which usually optimize routability by reallocating whitespace or net-based congestion removal, the proposed algorithm optimizes routability from three major aspects: (1) Pin density: Most existing works optimize routability based on net distribution, while our work considers both the density of pins and their routing directions; (2) Routing overflow optimization: Unlike most previous works that use whitespace allocation or net-based congestion removal to improve routability, our work optimizes routing overflow by a novel sigmoid function during global placement; (3) Macro porosity consideration: A virtual macro expansion technique is applied to consider the constrained routing resource incurred by big macros. Routability-driven legalization and detailed placement are also proposed to further optimize routing congestion. Experimental results show the effectiveness and efficiency of our proposed algorithm. Compared with the participating teams for the 2011 ACM ISPD Routability-Driven Placement Contest, our algorithm achieves the best average overflow and routed wirelength.