Multi-stack optimization for data-path chip (microprocessor) layout
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
A data path layout assembler for high performance DSP circuits
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
A timing-driven data path layout synthesis with integer programming
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
A signature based approach to regularity extraction
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Data path placement with regularity
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Regularity driven logic synthesis
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
ISPD 2006 Placement Contest: Benchmark Suite and Results
Proceedings of the 2006 international symposium on Physical design
Satisfying whitespace requirements in top-down placement
Proceedings of the 2006 international symposium on Physical design
mPL6: enhanced multilevel mixed-size placement
Proceedings of the 2006 international symposium on Physical design
FastPlace 3.0: A Fast Multilevel Quadratic Placement Algorithm with Placement Congestion Control
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Abacus: fast legalization of standard cell circuits with minimal movement
Proceedings of the 2008 international symposium on Physical design
Quantifying academic placer performance on custom designs
Proceedings of the 2011 international symposium on Physical design
TSV-aware analytical placement for 3D IC designs
Proceedings of the 48th Design Automation Conference
Routability-driven analytical placement for mixed-size circuit designs
Proceedings of the International Conference on Computer-Aided Design
Performance optimization using template mapping for datapath-intensive high-level synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Partitioning and Placement Technique for CMOS Gate Arrays
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Implementation and extensibility of an analytic placer
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Progress and challenges in VLSI placement research
Proceedings of the International Conference on Computer-Aided Design
Proceedings of the International Conference on Computer-Aided Design
Network flow based datapath bit slicing
Proceedings of the 2013 ACM international symposium on International symposium on physical design
Routability-driven placement for hierarchical mixed-size circuit designs
Proceedings of the 50th Annual Design Automation Conference
LatchPlanner: latch placement algorithm for datapath-oriented high-performance VLSI designs
Proceedings of the International Conference on Computer-Aided Design
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Datapath is one of the most important components in high performance circuit designs, such as microprocessors, as it is used to manipulate all data. For better performance, a datapath is usually placed with high regularity and compactness. Although cell placement has been studied extensively, not much work addresses the optimization of datapaths which are often treated as big macros. In this paper, we propose a structure-aware placement algorithm that can exploit the regular structures of datapath circuits and meanwhile leverage effective techniques to achieve high quality and scalability. Our algorithm applies a nonlinear optimization for wirelength minimization and a sigmoid based density model for density control in datapath circuits. Compared with state-of-the-art works, our algorithm can achieve the best structure-aware placement results efficiently.