Performance-driven placement of cell based IC's
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
A performance driven macro-cell placement algorithm
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
A data path layout assembler for high performance DSP circuits
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
CLIP: integer-programming-based optimal layout synthesis of 2D CMOS cells
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A regularity-driven fast gridless detailed router for high frequency datapath designs
Proceedings of the 2001 international symposium on Physical design
Data path placement with regularity
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Structure-aware placement for datapath-intensive circuit designs
Proceedings of the 49th Annual Design Automation Conference
| Hi-index | 0.00 |
We propose an efficient data path synthesis algorithm which generates bit-sliced layouts. Since data path circuits have special characteristics which are different from those of random logic circuits, the dedicated synthesis system is required for efficient layouts. Our main goal in the data path synthesis is to satisfy the timing constraints of circuits as well as to reduce layout areas. Timing-driven placement and over-the-cell routing techniques are developed to generate data path modules. Also, signal interfaces between bit-slices are carefully considered to further reduce layout areas. Our synthesis techniques take advantage of the common characteristics of data path structures under timing constraints and applies mixed integer linear programming approach to solve the problem. The superior results from our data path synthesis system are demonstrated through comparison with the layout results with the simulated annealing technique.