Introduction to VLSI Systems
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
SEFOP: a novel approach to data path module placement
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Accurate layout area and delay modeling for system level design
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Partitioning and floor-planning for data-path chip (microprocessor) layout
Integration, the VLSI Journal
Structure-aware placement for datapath-intensive circuit designs
Proceedings of the 49th Annual Design Automation Conference
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As data-path chips such as microprocessors and RISC chips become more complex, multiple stacks of data-path macros are required to implement the entire data-path. The physical decomposition of a chip into a single data-path stack, and control logic of random logic as in the past is not always feasible. This paper describes a special multi-stack structure, optimization techniques and algorithms to partition, place and wire the data-path macros in the form of the multi-stack structure, taking into account the connectivity of the entire chip logic (data-path, control logic, chip drivers, on-chip memory). The overall objective is: (1) to fit the circuits within the chip, (2) to ensure data-path wireability, including stack to random logic wireability, and (3) to minimize wire lengths for wireability and timing. A tool for automatic multi-stack optimization has been implemented and applied successfully to layout some high density data-path chips.