Multi-stack optimization for data-path chip (microprocessor) layout
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Introduction to VLSI Systems
KWIRE: a multiple-technology, user-reconfigurable wiring tool for VLSI
IBM Journal of Research and Development
An Improved Min-Cut Algonthm for Partitioning VLSI Networks
IEEE Transactions on Computers
Timing analysis of computer hardware
IBM Journal of Research and Development
A Hierarchical Global Wiring Algorithm for Custom Chip Design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Data-path chips are typically made up different types of objects such as data-path macros, control logic cells (e.g. standard-cell), memory arrays, and off-chip drivers. Each type of object is quite different than the other type in terms of size, shape, wiring blockage, and pin location characteristics, so existing placement tools have difficulties in handling all the objects in a single step. This paper presents a hierarchical method to floor-plan, and then place and route data-path chips. A chip is divided into a number of regions (terrains) each reserved for objects of the same type. The objects are first partitioned into the different terrains, then the objects in the same type of terrains are placed using tool designed for that terrain characteristics. Physical partitioning, integrated with global wiring and timing control, partitions the objects into different terrains, multi-stack placement places the data-path macros, standard-cell placement places the random logic and off-chip drivers; then followed by detailed wiring. Requirements on terrain size, terrain shape, wirability and timing are all considered throughout the various stages of the physical design. Results obtained on some actual chip designs are also presented.