A row-based cell placement method that utilizes circuit structural properties
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A general approach for regularity extraction in datapath circuits
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Regularity extraction via clan-based structural circuit decomposition
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
A regularity-driven fast gridless detailed router for high frequency datapath designs
Proceedings of the 2001 international symposium on Physical design
Data path placement with regularity
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Regularity driven logic synthesis
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Static Profile-Driven Compilation for FPGAs
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
A graph covering algorithm for a coarse grain reconfigurable system
Proceedings of the 2003 ACM SIGPLAN conference on Language, compiler, and tool for embedded systems
Efficient Logic Optimization Using Regularity Extraction
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Structure-aware placement for datapath-intensive circuit designs
Proceedings of the 49th Annual Design Automation Conference
Network flow based datapath bit slicing
Proceedings of the 2013 ACM international symposium on International symposium on physical design
LatchPlanner: latch placement algorithm for datapath-oriented high-performance VLSI designs
Proceedings of the International Conference on Computer-Aided Design
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Regularity extraction is an important step in the design flow of datapath-dominated circuits. This paper outlines a new method that automatically extracts regular structures from the netlist. The method is general enough to handle two types of designs: designs with structured cluster information for a portion of the datapath components that are identified at the HDL level; and designs with no such structured cluster information. The method analyzes the circuit connectivity and uses signature based approaches to recognize regularity.