Characterization and parameterized random generation of digital circuits
DAC '96 Proceedings of the 33rd annual Design Automation Conference
A signature based approach to regularity extraction
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Managing pipeline-reconfigurable FPGAs
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
A general approach for regularity extraction in datapath circuits
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Fast compilation for pipelined reconfigurable fabrics
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
PipeRench: a co/processor for streaming multimedia acceleration
ISCA '99 Proceedings of the 26th annual international symposium on Computer architecture
Speed and area tradeoffs in cluster-based FPGA architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Regularity driven logic synthesis
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
VPR: A new packing, placement and routing tool for FPGA research
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
CPR: A Configuration Profiling Tool
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
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We describe a static profiling methodology to extract hotspots from netlists. Hot-spots are small regular sub-circuits the optimization of which has a big impact on the final result. We have built a tool that can extract and characterize hot-spots from large netlists very quickly. The tool can be used to direct human attention on portions of circuits that need hand-optimization, as well as to automatically direct efforts of FPGA tools. We show impressive throughput improvements when compiling to the PipeRench reconfigurable architecture and use hot-spots to enable fast architectural design space exploration for FPGAs by predicting the FPGA CLB structure that produces the best final area-delay. Our prediction is fairly accurate and only takes a few hours as compared to weeks for an exhaustive analysis. We also demonstrate better results when targeting FPGAs with heterogeneous CLBs.