Circuit design of routing switches
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Efficient circuit clustering for area and power reduction in FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Static Profile-Driven Compilation for FPGAs
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
Mapping deep nested do-loop DSP algorithms to large scale FPGA array structures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Configurable Logic Architecture for Dynamic Hardware/Software Partitioning
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Dynamic FPGA routing for just-in-time FPGA compilation
Proceedings of the 41st annual Design Automation Conference
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
Analysis of the Effect of LUT Size on FPGA Area and Delay Using Theoretical Derivations
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Proceedings of the 41st annual Design Automation Conference
Via-configurable routing architectures and fast design mappability estimation for regular fabrics
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Perturb+mutate: Semisynthetic circuit generation for incremental placement and routing
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
EURASIP Journal on Advances in Signal Processing
Timing-driven nonuniform depopulation-based clustering
International Journal of Reconfigurable Computing - Special issue on selected papers from spl 2009 programmable logic and applications
Towards scalable FPGA CAD through architecture
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Triggered instructions: a control paradigm for spatially-programmed architectures
Proceedings of the 40th Annual International Symposium on Computer Architecture
Integration of Net-Length Factor with Timing- and Routability-Driven Clustering Algorithms
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
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One way to reduce the delay and area of field-programmable gate arrays (FPGAs) is to employ logic-cluster-based architectures, where a logic cluster is a group of logic elements connected with high-speed local interconnections. In this paper, we empirically evaluate FPGA architectures with logic clusters ranging in size from 1 to 20, and show that compared to architectures with size 1 clusters, architectures with size 8 clusters have 23% less delay (30% faster clock speed) and require 14% less area. We also show that FPGA architectures with large cluster sizes can significantly reduce design compile time-an increasingly important concern as the logic capacity of FPGA's rises. For example, an architecture that uses size 20 clusters requires seven times less compile time than an architecture with size 1 clusters.