Efficient Steiner tree construction based on spanning graphs
Proceedings of the 2003 international symposium on Physical design
Efficient Thermal Placement of Standard Cells in 3D ICs using a Force Directed Approach
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Multilevel generalized force-directed method for circuit placement
Proceedings of the 2005 international symposium on Physical design
mPL6: enhanced multilevel mixed-size placement
Proceedings of the 2006 international symposium on Physical design
A faster implementation of APlace
Proceedings of the 2006 international symposium on Physical design
Placement of 3D ICs with thermal and interlayer via considerations
Proceedings of the 44th annual Design Automation Conference
Thermal-Aware 3D IC Placement Via Transformation
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Abacus: fast legalization of standard cell circuits with minimal movement
Proceedings of the 2008 international symposium on Physical design
A multilevel analytical placement for 3D ICs
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
A study of Through-Silicon-Via impact on the 3D stacked IC layout
Proceedings of the 2009 International Conference on Computer-Aided Design
An analytical placer for mixed-size 3D placement
Proceedings of the 19th international symposium on Physical design
Implementation and extensibility of an analytic placer
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Scalable hierarchical floorplanning for fast physical prototyping of systems-on-chip
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
ComPLx: A Competitive Primal-dual Lagrange Optimization for Global Placement
Proceedings of the 49th Annual Design Automation Conference
Structure-aware placement for datapath-intensive circuit designs
Proceedings of the 49th Annual Design Automation Conference
Progress and challenges in VLSI placement research
Proceedings of the International Conference on Computer-Aided Design
An efficient wirelength model for analytical placement
Proceedings of the Conference on Design, Automation and Test in Europe
Routability-driven placement for hierarchical mixed-size circuit designs
Proceedings of the 50th Annual Design Automation Conference
Coupling-aware force driven placement of TSVs and shields in 3D-IC layouts
Proceedings of the 2014 on International symposium on physical design
| Hi-index | 0.00 |
Through-silicon vias (TSVs) are required for transmitting signals among different dies for the three-dimensional integrated circuit (3D IC) technology. The significant silicon areas occupied by TSVs bring critical challenges for 3D IC placement. Unlike most published 3D placement works that only minimize the number of TSVs during placement due to the limitations in their techniques, this paper proposes a new 3D cell placement algorithm which can additionally consider the sizes of TSVs and the physical positions for TSV insertion during placement. The algorithm consists of three stages: (1) 3D analytical global placement with density optimization and whitespace reservation for TSVs, (2) TSV insertion and TSV-aware legalization, and (3) layer-by-layer detailed placement. In particular, the global placement is based on a novel weighted-average wirelength model, giving the first model in the literature that can outperform the well-known log-sum-exp wirelength model theoretically and empirically. Further, 3D routing can easily be accomplished by traditional 2D routers since the physical positions of TSVs are determined during placement. Compared with state-of-the-art 3D cell placement works, our algorithm can achieve the best routed wirelength, TSV counts, and total silicon area, in shortest running time.