Multilevel hypergraph partitioning: applications in VLSI domain
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Consistent placement of macro-blocks using floorplanning and standard-cell placement
Proceedings of the 2002 international symposium on Physical design
Efficient Thermal Placement of Standard Cells in 3D ICs using a Force Directed Approach
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Multilevel generalized force-directed method for circuit placement
Proceedings of the 2005 international symposium on Physical design
A semi-persistent clustering technique for VLSI circuit placement
Proceedings of the 2005 international symposium on Physical design
Demystifying 3D ICs: The Pros and Cons of Going Vertical
IEEE Design & Test
A thermal-driven floorplanning algorithm for 3D ICs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Unification of partitioning, placement and floorplanning
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Interconnects in the third dimension: design challenges for 3D ICs
Proceedings of the 44th annual Design Automation Conference
Placement of 3D ICs with thermal and interlayer via considerations
Proceedings of the 44th annual Design Automation Conference
Thermal-Aware 3D IC Placement Via Transformation
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Efficient Thermal Aware Placement Approach Integrated with 3D DCT Placement Algorithm
ISQED '08 Proceedings of the 9th international symposium on Quality Electronic Design
A multilevel analytical placement for 3D ICs
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
The road to 3D EDA tool readiness
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
A Robust Mixed-Size Legalization and Detailed Placement Algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Highly Efficient Gradient Computation for Density-Constrained Analytical Placement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
TSV-aware analytical placement for 3D IC designs
Proceedings of the 48th Design Automation Conference
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Existing 3D placement techniques are mainly used for standard-cell circuits, while mixed-size placement is needed to support high-level functional units and intellectual property (IP) blocks. In this paper we present an analytical 3D placement method that is capable of placing mixed-size circuits. A multiple-stepsize scheme for the analytical solver is proposed to handle standard cells and macros differently for stability and efficiency. To relieve the difficulty of legalization, 3D floorplan-based initial solutions are used to guide the analytical solver. As far as we know, this is the first work that reports 3D placement results for mixed-size circuits. Our experiments show that the multiple-stepsize scheme is better than single-stepsize schemes in both quality and runtime. The experimental results on the ICCAD'04 mixed-size benchmarks show that the 4-tier 3D mixed-size placement can reduce the wirelength by 27% on average compared to 2D placement. The results also show that the 3D mixed-size placement achieves 5.3% shorter wirelength on average than the pseudo 3D placement with similar amount of through-silicon vias (TS vias).