A matrix synthesis approach to thermal placement
Proceedings of the 1997 international symposium on Physical design
Multilevel hypergraph partitioning: applications in VLSI domain
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Interconnect characteristics of 2.5-D system integration scheme
Proceedings of the 2001 international symposium on Physical design
Partition-driven standard cell thermal placement
Proceedings of the 2003 international symposium on Physical design
Proceedings of the 2004 international symposium on Physical design
Efficient Thermal Placement of Standard Cells in 3D ICs using a Force Directed Approach
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Temperature-aware global placement
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Design tools for 3-D integrated circuits
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
An efficient and effective detailed placement algorithm
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design
Cell-level placement for improving substrate thermal distribution
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimality and scalability study of existing placement algorithms
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A multi-story power delivery technique for 3D integrated circuits
Proceedings of the 13th international symposium on Low power electronics and design
Automated module assignment in stacked-Vdd designs for high-efficiency power delivery
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Congestion-aware power grid optimization for 3D circuits using MIM and CMOS decoupling capacitors
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
A multilevel analytical placement for 3D ICs
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Addressing thermal and power delivery bottlenecks in 3D circuits
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
The road to 3D EDA tool readiness
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
On the complexity of graph cuboidal dual problems for 3-D floorplanning of integrated circuit design
Proceedings of the 19th ACM Great Lakes symposium on VLSI
A study of Through-Silicon-Via impact on the 3D stacked IC layout
Proceedings of the 2009 International Conference on Computer-Aided Design
An analytical placer for mixed-size 3D placement
Proceedings of the 19th international symposium on Physical design
Complexity of 3-D floorplans by analysis of graph cuboidal dual hardness
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Three-dimensional integrated circuits (3D IC) floorplan and power/ground network co-synthesis
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Clock tree embedding for 3D ICs
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
TSV-aware analytical placement for 3D IC designs
Proceedings of the 48th Design Automation Conference
Thermal-aware cell and through-silicon-via co-placement for 3D ICs
Proceedings of the 48th Design Automation Conference
Through-silicon-via management during 3D physical design: when to add and how many?
Proceedings of the International Conference on Computer-Aided Design
Exploiting die-to-die thermal coupling in 3D IC placement
Proceedings of the 49th Annual Design Automation Conference
Obstacle aware routing in 3d integrated circuits
ADCONS'11 Proceedings of the 2011 international conference on Advanced Computing, Networking and Security
Thermal-aware P/G TSV planning for IR drop reduction in 3D ICs
Integration, the VLSI Journal
Rethinking the wirelength benefit of 3-D integration
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Thermal problems and limitations on interlayer via densities are important design constraints on three-dimensional integrated circuits (3D ICs), and need to be considered during global and detailed placement. Analytical and partitioning-based techniques are developed to explore the tradeoff between wirelength, interlayer via counts, and thermal effects. This method allows wirelengths to be minimized for any desired interlayer via density and temperatures to be reduced while minimizing deleterious effects on wirelength and interlayer via counts. Wirelength reductions within 2% of the optimal can be achieved using 46% fewer interlayer vias. Temperatures can be reduced by about 20% with only 1% higher wirelengths and 10% more interlayer vias.