Multilevel hypergraph partitioning: application in VLSI domain
DAC '97 Proceedings of the 34th annual Design Automation Conference
DAC '97 Proceedings of the 34th annual Design Automation Conference
NRG: global and detailed placement
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Performance of a new annealing schedule
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Can recursive bisection alone produce routable placements?
Proceedings of the 37th Annual Design Automation Conference
Interconnect characteristics of 2.5-D system integration scheme
Proceedings of the 2001 international symposium on Physical design
Dragon2000: standard-cell placement tool for large industry circuits
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Gravity: Fast placement for 3-D VLSI
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Improving Simulated Annealing Placement by Applying Random and Greedy Mixed Perturbations
SBCCI '03 Proceedings of the 16th symposium on Integrated circuits and systems design
Almost optimum placement legalization by minimum cost flow and dynamic programming
Proceedings of the 2004 international symposium on Physical design
Efficient Thermal Placement of Standard Cells in 3D ICs using a Force Directed Approach
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Demystifying 3D ICs: The Pros and Cons of Going Vertical
IEEE Design & Test
Placement and Routing in 3D Integrated Circuits
IEEE Design & Test
Three-dimensional place and route for FPGAs
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Placement of 3D ICs with thermal and interlayer via considerations
Proceedings of the 44th annual Design Automation Conference
Cell placement on graphics processing units
Proceedings of the 20th annual conference on Integrated circuits and systems design
Three-dimensional Integrated Circuit Design
Three-dimensional Integrated Circuit Design
A low power 3D integrated FFT engine using hypercube memory division
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Low-Power Hypercube Divided Memory FFT Engine Using 3D Integration
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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This paper presents a quadratic placement algorithm to be applied for 3D circuits. We formulate the 3D problem to control the area balance and the number of 3D-Vias between tiers. We introduce the z-Cell Shifting operation in order to control the area balance. We also define a new operation for the refinement of the solution called 3D Iterative Refinement, that has a control statement to avoid excessive number of 3D-Vias in order to keep the feasibility of our placement solution. After quadratic placement, we move to the placement legalization that is based on min-cost max flow and Simulated Annealing. For detailed placement refinement, we apply Simulated Annealing without cell migration between tiers. Experimental results show that our placement flow targeting one tier is comparable to academic tools such as FastPlace, Capo and Dragon in wire length and running time when targeting a single tier. On multiple tiers, we can reduce the average wire length from 7% (2 tiers) to 32% (5 tiers) and worst wire length by 26% (2 tiers) to 52% (5 tiers). The number of 3D-Vias obtained is feasible since the area overhead introduced is always below 10%.