SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design
Improving simulated annealing-based FPGA placement with directed moves
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper presents an improvement to placement using Simulated Annealing by applying a mix of greedy perturbations with the traditional random perturbations. The used greedy movements are based on a force-directed technique focused on wire length optimization. By analyzing cost curves related to running time, it is possible to see that our technique can converge faster than with any isolated technique. The experiment results show that our mixed perturbation schema outperforms Timberwolf [1] random perturbation approach by 13, 18% (wire length) and 21, 36% (maximum wire congestion) in the best case.