A low power 3D integrated FFT engine using hypercube memory division

Authors:
Thorlindur Thorolfsson;Nariman Moezzi-Madani;Paul D. Franzon
Affiliations:
North Carolina State University, Raleigh, NC, USA;North Carolina State University, Raleigh, NC, USA;North Carolina State University, Raleigh, NC, USA
Venue:
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Year:
2009

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Abstract

In this paper we demonstrate a floating point FFT processor that leverages both 3D integration and a hypercube memory division scheme to reduce the power consumption of a 1024 point FFT down to 4.227 μJ. The hypercube memory division scheme lowers the energy per memory access by 59.2% while only increasing the total area required by 16.8%, while using 3D integration reduces the logic power by 5.2%. For comparison, we analyze the amount of power and wire length reduction that can be expected from 3D integration for normal digital logic circuits.