One-processor scheduling with symmetric earliness and tardiness penalties
Mathematics of Operations Research
Simulated annealing for VLSI design
Simulated annealing for VLSI design
NRG: global and detailed placement
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Faster optimal single-row placement with fixed ordering
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Algorithms for detailed placement of standard cells
Proceedings of the conference on Design, automation and test in Europe
Mongrel: hybrid techniques for standard cell placement
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Dragon2000: standard-cell placement tool for large industry circuits
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Guided Local Search for Final Placement in VLSI Design
Journal of Heuristics
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Diffusion-based placement migration
Proceedings of the 42nd annual Design Automation Conference
Faster and better global placement by a new transportation algorithm
Proceedings of the 42nd annual Design Automation Conference
A robust detailed placement for mixed-size IC designs
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
mPL6: enhanced multilevel mixed-size placement
Proceedings of the 2006 international symposium on Physical design
Computational geometry based placement migration
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Architecture and details of a high quality, large-scale analytical placer
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Constraint-driven floorplan repair
Proceedings of the 43rd annual Design Automation Conference
SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design
A network-flow approach to timing-driven incremental placement for ASICs
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
SafeResynth: A new technique for physical synthesis
Integration, the VLSI Journal
Constraint-driven floorplan repair
ACM Transactions on Design Automation of Electronic Systems (TODAES)
History-based VLSI legalization using network flow
Proceedings of the 47th Design Automation Conference
A hierarchical bin-based legalizer for standard-cell designs with minimal disturbance
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Multi-stage detailed placement algorithm for large-scale mixed-mode layout design
ICCSA'05 Proceedings of the 2005 international conference on Computational Science and Its Applications - Volume Part IV
LatchPlanner: latch placement algorithm for datapath-oriented high-performance VLSI designs
Proceedings of the International Conference on Computer-Aided Design
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VLSI placement tools usually work in two steps: First, the cells that have to be placed are roughly spread out over the chip area ignoring disjointness (global placement). Then, in a second step, the cells are moved to their final position such that all overlaps are removed and all additional constraints are met (detailed placement or legalization).We consider algorithms for legalization. In particular, we analyze a generic legalization algorithm based on minimum cost flows and dynamic programming. Specializations are being used in industry for many years, and an improved version was proposed very recently in [2]. The objective of all these algorithms is to minimize the weighted sum of (squared) movements, i.e. they assume the placement to be already optimized except for not being legal.To evaluate results, we propose two different lower bounds for the legalization problem, one based on linear assignment, and the other one based on an integer linear programming relaxation. We prove that the second lower bound is always at least as good as the first one. We also show how to compute the bounds efficiently. We then give an extensive experimental analysis of the algorithms and the lower bounds by testing them on a set of recent industrial ASICs with up to 2.4 million cells. In particular, we show that the gap between the new algorithm and the better lower bound is usually less than 10 percent. This proves that the legalization problem is solved almost optimally.Besides (weighted) total (squared) movement, we also consider various other objectives like wirelength, timing, and routability. Our experiments demonstrate that minimizing total (weighted, squared) movement has almost no negative effect on the timing properties, routability and netlength. Therefore the new algorithm will help in overall design closure.