Post-placement residual-overlap removal with minimal movement
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Floorplan representations: Complexity and connections
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A Unified Method to Handle Different Kinds of Placement Constraints in Floorplan Design
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Almost optimum placement legalization by minimum cost flow and dynamic programming
Proceedings of the 2004 international symposium on Physical design
Recursive bisection based mixed block placement
Proceedings of the 2004 international symposium on Physical design
Diffusion-based placement migration
Proceedings of the 42nd annual Design Automation Conference
A robust detailed placement for mixed-size IC designs
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Multi-level placement for large-scale mixed-size IC designs
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Fast floorplanning by look-ahead enabled recursive bipartitioning
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Robust mixed-size placement under tight white-space constraints
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Architecture and details of a high quality, large-scale analytical placer
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Constraint-driven floorplan repair
Proceedings of the 43rd annual Design Automation Conference
Fixed-outline floorplanning: enabling hierarchical design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Assembling 2D blocks into 3D chips
Proceedings of the 2011 international symposium on Physical design
Scalable hierarchical floorplanning for fast physical prototyping of systems-on-chip
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
Progress and challenges in VLSI placement research
Proceedings of the International Conference on Computer-Aided Design
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In this work, we propose a new and efficient approach to the floorplan repair problem, where violated design constraints are satisfied by applying small changes to an existing rough floorplan. Such a floorplan can be produced by a human designer, a scalable placement algorithm, or result from engineering adjustments to an existing floorplan. In such cases, overlapping modules must be separated, and others may need to be repositioned to satisfy additional requirements. Our algorithmic framework uses an expressive graph-based encoding of constraints which can reflect fixed-outline, region, proximity and alignment constraints. By tracking the implications of existing constraints, we resolve violations by imposing gradual modifications to the floorplan, in an attempt to preserve the characteristics of its initial design. Empirically, our approach is effective at removing overlaps and repairing violations that may occur when design constraints are acquired and imposed dynamically.