Rectangle-packing-based module placement
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Multilevel hypergraph partitioning: application in VLSI domain
DAC '97 Proceedings of the 34th annual Design Automation Conference
Congestion driven quadratic placement
DAC '98 Proceedings of the 35th annual Design Automation Conference
Can recursive bisection alone produce routable placements?
Proceedings of the 37th Annual Design Automation Conference
Fast floorplanning for effective prediction and construction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Consistent placement of macro-blocks using floorplanning and standard-cell placement
Proceedings of the 2002 international symposium on Physical design
Implementation and extensibility of an analytic placer
Proceedings of the 2004 international symposium on Physical design
Proceedings of the 2004 international symposium on Physical design
Recursive bisection based mixed block placement
Proceedings of the 2004 international symposium on Physical design
Large-scale placement by grid-warping
Proceedings of the 41st annual Design Automation Conference
Placement feedback: a concept and method for better min-cut placements
Proceedings of the 41st annual Design Automation Conference
On Whitespace and Stability in Mixed-Size Placement and Physical Synthesis
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Multilevel generalized force-directed method for circuit placement
Proceedings of the 2005 international symposium on Physical design
The ISPD2005 placement contest and benchmark suite
Proceedings of the 2005 international symposium on Physical design
An analytic placer for mixed-size placement and timing-driven placement
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Unification of partitioning, placement and floorplanning
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Multi-level placement for large-scale mixed-size IC designs
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Fast floorplanning by look-ahead enabled recursive bipartitioning
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
An effective congestion-driven placement framework
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Routability-driven white space allocation for fixed-die standard-cell placement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A robust detailed placement for mixed-size IC designs
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Solving hard instances of floorplacement
Proceedings of the 2006 international symposium on Physical design
Satisfying whitespace requirements in top-down placement
Proceedings of the 2006 international symposium on Physical design
Constraint-driven floorplan repair
Proceedings of the 43rd annual Design Automation Conference
Mixed-size placement with fixed macrocells using grid-warping
Proceedings of the 2007 international symposium on Physical design
Constraint-driven floorplan repair
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Solving modern mixed-size placement instances
Integration, the VLSI Journal
What makes a design difficult to route
Proceedings of the 19th international symposium on Physical design
ComPLx: A Competitive Primal-dual Lagrange Optimization for Global Placement
Proceedings of the 49th Annual Design Automation Conference
Progress and challenges in VLSI placement research
Proceedings of the International Conference on Computer-Aided Design
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A novel and very simple correct-by-construction top-down methodology for high-utilization mixed-size placement is presented. The Polarbear algorithm combines recursive cut-size-driven partitioning with fast and scalable legalization of every placement subproblem generated by every partitioning. The feedback provided by the legalizer at all stages of partitioning improves final placement quality significantly on standard IBM benchmarks and dramatically on low-white-space adaptations of them. Compared to Feng Shui 5.1 and Capo 9.3, Polarbear is the only tool that can consistently find high-quality placements for benchmarks with less than 5% white space. With white space at 5%, Polarbear beats Capo 9.3 by 10% in average total wirelength while Feng Shui 5.1 frequently fails to find legal placements altogether. With 20% white space, POLARBEAR still beats Capo 9.3 by 1% and Feng Shui 5.1 by 1% in average total wirelength, in comparable run times.