A New Effective Congestion Model in Floorplan Design
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Large-Scale Circuit Placement: Gap and Promise
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Accurate and efficient flow based congestion estimation in floorplanning
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Probabilistic congestion model considering shielding for crosstalk reduction
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Via-configurable routing architectures and fast design mappability estimation for regular fabrics
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Robust mixed-size placement under tight white-space constraints
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Novel full-chip gridless routing considering double-via insertion
Proceedings of the 43rd annual Design Automation Conference
Via-configurable routing architectures and fast design mappability estimation for regular fabrics
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
FastRoute: a step to integrate global routing into placement
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
BoxRouter 2.0: architecture and implementation of a hybrid and robust global router
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
BoxRouter 2.0: A hybrid and robust global router with layer assignment for routability
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A Performance-Driven Multilevel Framework for the X-Based Full-Chip Router
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
PIXAR: A performance-driven X-architecture router based on a novel multilevel framework
Integration, the VLSI Journal
What makes a design difficult to route
Proceedings of the 19th international symposium on Physical design
Ripple: an effective routability-driven placer by iterative cell movement
Proceedings of the International Conference on Computer-Aided Design
Proceedings of the 49th Annual Design Automation Conference
The DAC 2012 routability-driven placement contest and benchmark suite
Proceedings of the 49th Annual Design Automation Conference
SRP: simultaneous routing and placement for congestion refinement
Proceedings of the 2013 ACM international symposium on International symposium on physical design
Ripple 2.0: high quality routability-driven placement via global router integration
Proceedings of the 50th Annual Design Automation Conference
Placement-driven partitioning for congestion mitigation in monolithic 3D IC designs
Proceedings of the 2014 on International symposium on physical design
| Hi-index | 0.03 |
We present a fast but reliable way to detect routing criticalities in very large scale integration chips. In addition, we show how this congestion estimation can be incorporated into a partitioning based placement algorithm. Different to previous approaches, we do not rerun parts of the placement algorithm or apply a postplacement optimization, but we use our congestion estimator for a dynamic avoidance of routability problems in one single run of the placement algorithm. Computational experiments on chips with up to 1300000 cells are presented. The framework reduces the usage of the most critical routing edges by 9.0% on average, the running time increase for the placement is about 8.7%. However, due to the smaller congestion, the running time of routing tools can be decreased drastically, so the total time for placement and (global) routing is decreased by 47% on average.