The X architecture: not your father's diagonal wiring
SLIP '02 Proceedings of the 2002 international workshop on System-level interconnect prediction
A novel framework for multilevel routing considering routability and performance
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
An enhanced multilevel routing system
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Track assignment: a desirable intermediate step between global routing and detailed routing
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Wire routing by optimizing channel assignment within large apertures
DAC '71 Proceedings of the 8th Design Automation Workshop
A New Effective Congestion Model in Floorplan Design
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Multilevel routing with antenna avoidance
Proceedings of the 2004 international symposium on Physical design
A Fast Crosstalk- and Performance-Driven Multilevel Routing System
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
Multilevel full-chip routing for the X-based architecture
Proceedings of the 42nd annual Design Automation Conference
Estimating routing congestion using probabilistic analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An effective congestion-driven placement framework
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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As technology advances into the nanometer territory, the interconnect delay has become a first-order effect on chip performance. To handle this effect, the X-architecture has been proposed for high-performance integrated circuits. In this paper, we present a performance-driven multilevel framework for the X-based full-chip router. To fully consider performance-driven routing and take advantage of the X-architecture, we apply a novel multilevel routing framework, which adopts a four-stage technique of a trial routing stage, followed by a top-down uncoarsening stage, with an intermediate track routing stage, and then followed by a bottom-up coarsening stage. Compared with the state-of-the-art work, we achieve 100% routing completion for all circuits while reduced the net delay.