On Whitespace and Stability in Mixed-Size Placement and Physical Synthesis

• Authors: Saurabh N. Adya;Igor L. Markov;Paul G. Villarrubia
• Venue: Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
• Year: 2003

In the context of physical synthesis, large-scale standard-cell placementalgorithms must facilitate incremental changes to layout, bothlocal and global. In particular, flexible gate sizing, net buffering anddetail placement require a certain amount of unused space in everyregion of the die. The need for "local" whitespace is further emphasizedby temperature and power-density limits. Another requirement,the stability of placement results from run to run, is importantto the convergence of physical synthesis loops. Indeed, logic resynthesistargetting local congestion in a given placement or particularcritical paths may be irrelevant for another placement produced bythe same or a different layout tool.In this work we offer solutions to the above problems. We showhow to tie the results of a placer to a previously existing placement,and yet leave room for optimization. In our experiments this techniqueproduces placements with similar congestion maps. We alsoshow how to trade-off wirelength for routability by manipulatingwhitespace. Empirically, our techniques improve circuit delay ofsparse layouts in conjunction with physical synthesis.In the context of earlier proposed techniques for mixed-size placement, we tune a state-of-the-art recursive bisection placer to betterhandle regular netlists that offer a convenient way to representmemories, datapaths and random-logic IP blocks. These modificationsand better whitespace distribution improve results on recentmixed-size placement benchmarks.