An effective congestion driven placement framework

Authors:
Ulrich Brenner;André Rohe
Affiliations:
University of Bonn, Germany;University of Bonn, Germany
Venue:
Proceedings of the 2002 international symposium on Physical design
Year:
2002

Citing 19
Cited 36

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Abstract

We present a fast but reliable way to detect routing criticalities in VLSI chips. In addition, we show how this congestion estimation can be incorporated into a partitioning based placement algorithm. Different to previous approaches, we do not rerun parts of the placement algorithm or apply a post-placement optimization, but we use our congestion estimator for a dynamic avoidance of routability problems in one single run of the placement algorithm. Computational experiments on chips with up to 1,300,000 cells are presented: The framework reduces the usage of the most critical routing edges by 9.0% on average, the running time increase for the placement is about 8.7%. However, due to the smaller congestion, the running time of routing tools can be decreased drastically, so the total time for placement and (global) routing is decreased by 47% on average.