RISA: accurate and efficient placement routability modeling
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Congestion driven quadratic placement
DAC '98 Proceedings of the 35th annual Design Automation Conference
Multi-center congestion estimation and minimization during placement
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Estimating routing congestion using probabilistic analysis
Proceedings of the 2001 international symposium on Physical design
Congestion estimation during top-down placement
Proceedings of the 2001 international symposium on Physical design
An effective congestion driven placement framework
Proceedings of the 2002 international symposium on Physical design
Routability driven white space allocation for fixed-die standard-cell placement
Proceedings of the 2002 international symposium on Physical design
On metrics for comparing routability estimation methods for FPGAs
Proceedings of the 39th annual Design Automation Conference
Mongrel: hybrid techniques for standard cell placement
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Dragon2000: standard-cell placement tool for large industry circuits
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
VPR: A new packing, placement and routing tool for FPGA research
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
Performance-driven simultaneous placement and routing for FPGA's
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Hierarchical whitespace allocation in top-down placement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Seeing the forest and the trees: Steiner wirelength optimization in placemen
Proceedings of the 2006 international symposium on Physical design
Trunk decomposition based global routing optimization
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
IPR: an integrated placement and routing algorithm
Proceedings of the 44th annual Design Automation Conference
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The main goal of This work is to develop deeper insights into viable placement-level optimization of routing. Two primary contributions are made. First, an experimental framework in which the viability of predictive models of routing congestion for optimization during detailed placement can be evaluated, is developed. The main criteria of consideration in these experiments is how (un)reliably various models from the literature detect routing hot-spots. We conclude that such models appear to be too unreliable for detailed placement optimization. Second, motivated by the first result, we present a unified combinatorial framework in which cell placement and exact routing structures are captured and optimized; the framework relies on the trunk-decomposition of global routing structures and optimization is performed by a generalized optimal interleaving algorithm (Hur and Lillis, 2000). A proof of concept implementation of this framework is studied in the FPGA domain. The technique can reduce the number of channels at maximum density by almost 45% on average with maximum reduction of 68% for optimized global routing.