RISA: accurate and efficient placement routability modeling
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Congestion driven quadratic placement
DAC '98 Proceedings of the 35th annual Design Automation Conference
On the behavior of congestion minimization during placement
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Multi-center congestion estimation and minimization during placement
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Modeling and minimization of routing congestion
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
A new congestion-driven placement algorithm based on cell inflation
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
An effective congestion driven placement framework
Proceedings of the 2002 international symposium on Physical design
Proceedings of the 2003 international workshop on System-level interconnect prediction
Accurate pseudo-constructive wirelength and congestion estimation
Proceedings of the 2003 international workshop on System-level interconnect prediction
Iterative Methods for Sparse Linear Systems
Iterative Methods for Sparse Linear Systems
Probabilistic congestion prediction
Proceedings of the 2004 international symposium on Physical design
Is probabilistic congestion estimation worthwhile?
Proceedings of the 2005 international workshop on System level interconnect prediction
Routability-driven placement and white space allocation
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Congestion driven incremental placement algorithm for standard cell layout
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
An efficient and effective detailed placement algorithm
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
On whitespace and stability in physical synthesis
Integration, the VLSI Journal
Fast and accurate routing demand estimation for efficient routability-driven placement
Proceedings of the conference on Design, automation and test in Europe
IPR: an integrated placement and routing algorithm
Proceedings of the 44th annual Design Automation Conference
FastPlace 3.0: A Fast Multilevel Quadratic Placement Algorithm with Placement Congestion Control
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Proceedings of the 45th annual Design Automation Conference
NTHU-Route 2.0: a fast and stable global router
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Multi-layer global routing considering via and wire capacities
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
FastRoute 4.0: global router with efficient via minimization
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Handbook of Algorithms for Physical Design Automation
Handbook of Algorithms for Physical Design Automation
CROP: fast and effective congestion refinement of placement
Proceedings of the 2009 International Conference on Computer-Aided Design
CRISP: congestion reduction by iterated spreading during placement
Proceedings of the 2009 International Conference on Computer-Aided Design
What makes a design difficult to route
Proceedings of the 19th international symposium on Physical design
Completing high-quality global routes
Proceedings of the 19th international symposium on Physical design
A parallel integer programming approach to global routing
Proceedings of the 47th Design Automation Conference
Multi-threaded collision-aware global routing with bounded-length maze routing
Proceedings of the 47th Design Automation Conference
An enhanced global router with consideration of general layer directives
Proceedings of the 2011 international symposium on Physical design
VLSI Physical Design: From Graph Partitioning to Timing Closure
VLSI Physical Design: From Graph Partitioning to Timing Closure
GLADE: a modern global router considering layer directives
Proceedings of the International Conference on Computer-Aided Design
SimPL: an effective placement algorithm
Proceedings of the International Conference on Computer-Aided Design
On wirelength estimations for row-based placement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Congestion minimization during placement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Congestion estimation during top-down placement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Routability-driven white space allocation for fixed-die standard-cell placement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
RBI: Simultaneous Placement and Routing Optimization Technique
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Seeing the Forest and the Trees: Steiner Wirelength Optimization in Placement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
MAPLE: multilevel adaptive placement for mixed-size designs
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
Proceedings of the 49th Annual Design Automation Conference
ComPLx: A Competitive Primal-dual Lagrange Optimization for Global Placement
Proceedings of the 49th Annual Design Automation Conference
The DAC 2012 routability-driven placement contest and benchmark suite
Proceedings of the 49th Annual Design Automation Conference
Progress and challenges in VLSI placement research
Proceedings of the International Conference on Computer-Aided Design
Proceedings of the International Conference on Computer-Aided Design
A fast maze-free routing congestion estimator with hybrid unilateral monotonic routing
Proceedings of the International Conference on Computer-Aided Design
Planning for local net congestion in global routing
Proceedings of the 2013 ACM international symposium on International symposium on physical design
SRP: simultaneous routing and placement for congestion refinement
Proceedings of the 2013 ACM international symposium on International symposium on physical design
Case study for placement solutions in ispd11 and dac12 routability-driven placement contests
Proceedings of the 2013 ACM international symposium on International symposium on physical design
SimPL: an algorithm for placing VLSI circuits
Communications of the ACM
Sub-quadratic objectives in quadratic placement
Proceedings of the Conference on Design, Automation and Test in Europe
Taming the complexity of coordinated place and route
Proceedings of the 50th Annual Design Automation Conference
Routability-driven placement for hierarchical mixed-size circuit designs
Proceedings of the 50th Annual Design Automation Conference
Ripple 2.0: high quality routability-driven placement via global router integration
Proceedings of the 50th Annual Design Automation Conference
Optimization of placement solutions for routability
Proceedings of the 50th Annual Design Automation Conference
A study on unroutable placement recognition
Proceedings of the 2014 on International symposium on physical design
MIP-based detailed placer for mixed-size circuits
Proceedings of the 2014 on International symposium on physical design
POLAR: placement based on novel rough legalization and refinement
Proceedings of the International Conference on Computer-Aided Design
ISPD 2014 benchmarks with sub-45nm technology rules for detailed-routing-driven placement
Proceedings of the 2014 on International symposium on physical design
Techniques for scalable and effective routability evaluation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Highly-optimized placements may lead to irreparable routing congestion due to inadequate models of modern interconnect stacks and the impact of partial routing obstacles. Additional challenges in routability-driven placement include scalability to large netlists and limiting the complexity of software integration. Addressing these challenges, we develop lookahead routing to give the placer advance, firsthand knowledge of trouble spots, not distorted by crude congestion models. We also extend global placement to (i) spread cells apart in congested areas, and (ii) move cells together in less-congested areas to ensure short, routable interconnects and moderate runtime. While previous work adds isolated steps to global placement, our SIMultaneous PLace-and-Route tool SimPLR integrates a layer- and via-aware global router into a leading-edge, force-directed placer. The complexity of integration is mitigated by careful design of simple yet effective optimizations. On the ISPD 2011 Contest Benchmark Suite, with the official evaluation protocol, SimPLR outperforms every contestant on every benchmark.