Multi-center congestion estimation and minimization during placement
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Fast and accurate routing demand estimation for efficient routability-driven placement
Proceedings of the conference on Design, automation and test in Europe
IPR: an integrated placement and routing algorithm
Proceedings of the 44th annual Design Automation Conference
BoxRouter 2.0: A hybrid and robust global router with layer assignment for routability
ACM Transactions on Design Automation of Electronic Systems (TODAES)
NTHU-Route 2.0: a fast and stable global router
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
FastRoute 4.0: global router with efficient via minimization
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
High-performance global routing with fast overflow reduction
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
CRISP: congestion reduction by iterated spreading during placement
Proceedings of the 2009 International Conference on Computer-Aided Design
RegularRoute: an efficient detailed router with regular routing patterns
Proceedings of the 2011 international symposium on Physical design
The ISPD-2011 routability-driven placement contest and benchmark suite
Proceedings of the 2011 international symposium on Physical design
A SimPLR method for routability-driven placement
Proceedings of the International Conference on Computer-Aided Design
Ripple: an effective routability-driven placer by iterative cell movement
Proceedings of the International Conference on Computer-Aided Design
Routability-driven analytical placement for mixed-size circuit designs
Proceedings of the International Conference on Computer-Aided Design
MGR: multi-level global router
Proceedings of the International Conference on Computer-Aided Design
Congestion analysis for global routing via integer programming
Proceedings of the International Conference on Computer-Aided Design
GLADE: a modern global router considering layer directives
Proceedings of the International Conference on Computer-Aided Design
GLARE: global and local wiring aware routability evaluation
Proceedings of the 49th Annual Design Automation Conference
High-Performance Routing at the Nanometer Scale
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ISPD 2014 benchmarks with sub-45nm technology rules for detailed-routing-driven placement
Proceedings of the 2014 on International symposium on physical design
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Local nets are a major contributing factor to mismatch between the global routing (GR) and detailed routing (DR) stages. A local net has all its terminals inside one global cell (gcell) and is traditionally ignored during global routing. This work offers two contributions in order to estimate and manage the local nets at the GR stage. First, a procedure is given to generate gcells of non-uniform size in order to reduce the number of local nets and thus the cumulative error associated with ignoring or approximating them. Second, we approximate the resource usage of local nets at the GR stage by introducing a capacity for each gcell in the GR graph. With these two complementary approaches, we offer a mathematical model for the congestion-aware GR problem that captures local congestion with non-uniform gcells along with other complicating factors of modern designs including variable wire sizes, routing blockages, and virtual pins. A practical routing procedure is presented based on the mathematical model that can solve large industry instances. This procedure is integrated with the CGRIP congestion analysis tool. In the experiments, we evaluate our techniques in planning for local nets during GR while accounting for other sources of congestion using the ISPD11 benchmarks.