A novel framework for multilevel full-chip gridless routing
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
FastRoute 2.0: A High-quality and Efficient Global Router
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
High-performance routing at the nanometer scale
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
BoxRouter 2.0: architecture and implementation of a hybrid and robust global router
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
NTHU-Route 2.0: a fast and stable global router
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
FastRoute 4.0: global router with efficient via minimization
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
High-performance global routing with fast overflow reduction
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Robust layer assignment for via optimization in multi-layer global routing
Proceedings of the 2009 international symposium on Physical design
GRIP: scalable 3D global routing using integer programming
Proceedings of the 46th Annual Design Automation Conference
Multi-threaded collision-aware global routing with bounded-length maze routing
Proceedings of the 47th Design Automation Conference
MARS-a multilevel full-chip gridless routing system
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
FLUTE: Fast Lookup Table Based Rectilinear Steiner Minimal Tree Algorithm for VLSI Design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A fast maze-free routing congestion estimator with hybrid unilateral monotonic routing
Proceedings of the International Conference on Computer-Aided Design
Planning for local net congestion in global routing
Proceedings of the 2013 ACM international symposium on International symposium on physical design
A fast and scalable multidimensional multiple-choice knapsack heuristic
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special Section on Networks on Chip: Architecture, Tools, and Methodologies
A study on unroutable placement recognition
Proceedings of the 2014 on International symposium on physical design
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Global routing faces an increasing problem size and urgent demand on improvement in solution quality. Despite of the recent developments of global routers, there exist only two types of choices: slow 3D routers with good solution quality or efficient 2D routers with relatively poor solution quality. We propose a multi-level 3D global router called MGR to fill the gap. MGR resorts to an efficient multi-level framework to reroute nets in the congested region on the 3D grid graph. Routing on the coarsened grid graph speeds up the global router while 3D routing introduces less vias. The powerful multi-level rerouting framework wraps three innovative routing techniques together: adaptive resource reservation in coarsening process, a new 3-terminal maze routing algorithm and network flow based solution propagation in uncoarsening process. As a result, MGR can achieve the solution quality close to 3D routers with comparable runtime of 2D routers.