ISPD 2014 benchmarks with sub-45nm technology rules for detailed-routing-driven placement

  • Authors:

  • Vladimir Yutsis;Ismail S. Bustany;David Chinnery;Joseph R. Shinnerl;Wen-Hao Liu

  • Affiliations:

  • Mentor Graphics Corporation, Fremont, CA, USA;Mentor Graphics Corporation, Fremont, CA, USA;Mentor Graphics Corporation, Fremont, CA, USA;Mentor Graphics Corporation, Fremont, CA, USA;National Tsing Hua University, Hsinchu, Taiwan Roc

  • Venue:
  • Proceedings of the 2014 on International symposium on physical design
  • Year:
  • 2014

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Abstract

The public release of realistic industrial placement benchmarks by IBM and Intel Corporations from 1998--2013 has been crucial to the progress in physical-design algorithms during those years. Direct comparisons of academic tools on these test cases, including widely publicized contests, have spurred researchers to discover faster, more scalable algorithms with significantly improved quality of results. Nevertheless, close examination of these benchmarks reveals that the removal of important physical data from them prior to release now presents a serious obstacle to any accurate appraisal of the detailed routability of their placements. Recent studies suggest that academic placement algorithms may lack sufficient awareness of the pin geometry and routing rules missing from these benchmarks to adequately address the challenge of computing routable placements at 28nm-process technologies and below. In this article, the reconstitution of the existing benchmarks via the injection of realistic yet fictitious pin data and routing rules is described. The enhanced benchmarks enable more meaningful comparisons of new placement algorithms by industrial detailed routing, beginning with the 2014 ISPD placement contest.