Robust partitioning for hardware-accelerated functional verification
Proceedings of the 48th Design Automation Conference
A SimPLR method for routability-driven placement
Proceedings of the International Conference on Computer-Aided Design
Algorithmic tuning of clock trees and derived non-tree structures
Proceedings of the International Conference on Computer-Aided Design
MDE-based FPGA physical design: fast model-driven prototyping with Smalltalk
Proceedings of the International Workshop on Smalltalk Technologies
ComPLx: A Competitive Primal-dual Lagrange Optimization for Global Placement
Proceedings of the 49th Annual Design Automation Conference
Progress and challenges in VLSI placement research
Proceedings of the International Conference on Computer-Aided Design
Multiobjective optimization of deadspace, a critical resource for 3D-IC integration
Proceedings of the International Conference on Computer-Aided Design
Electromigration and its impact on physical design in future technologies
Proceedings of the 2013 ACM international symposium on International symposium on physical design
Proceedings of the 2013 ACM international symposium on International symposium on physical design
SimPL: an algorithm for placing VLSI circuits
Communications of the ACM
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
ClockPUF: physical unclonable functions based on clock networks
Proceedings of the Conference on Design, Automation and Test in Europe
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Design and optimization of integrated circuits are essential to the creation of new semiconductor chips, and physical optimizations are becoming more prominent as a result of semiconductor scaling. Modern chip design has become so complex that it is largely performed by specialized software, which is frequently updated to address advances in semiconductor technologies and increased problem complexities. A user of such software needs a high-level understanding of the underlying mathematical models and algorithms. On the other hand, a developer of such software must have a keen understanding of computer science aspects, including algorithmic performance bottlenecks and how various algorithms operate and interact. VLSI Physical Design: From Graph Partitioning to Timing Closure introduces and compares algorithms that are used during the physical design phase of integrated-circuit design, wherein a geometric chip layout is produced starting from an abstract circuit design. The emphasis is on essential and fundamental techniques, ranging from hypergraph partitioning and circuit placement to timing closure.