Controlled Physical Random Functions
ACSAC '02 Proceedings of the 18th Annual Computer Security Applications Conference
Physical unclonable functions for device authentication and secret key generation
Proceedings of the 44th annual Design Automation Conference
FPGA Intrinsic PUFs and Their Use for IP Protection
CHES '07 Proceedings of the 9th international workshop on Cryptographic Hardware and Embedded Systems
Efficient Helper Data Key Extractor on FPGAs
CHES '08 Proceeding sof the 10th international workshop on Cryptographic Hardware and Embedded Systems
Techniques for Design and Implementation of Secure Reconfigurable PUFs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Power-Up SRAM State as an Identifying Fingerprint and Source of True Random Numbers
IEEE Transactions on Computers
Low-Overhead Implementation of a Soft Decision Helper Data Algorithm for SRAM PUFs
CHES '09 Proceedings of the 11th International Workshop on Cryptographic Hardware and Embedded Systems
Proceedings of the 46th Annual Design Automation Conference
Secure and Robust Error Correction for Physical Unclonable Functions
IEEE Design & Test
Proceedings of the 47th Design Automation Conference
History mechanism supported differential evolution for chess evaluation function tuning
Soft Computing - A Fusion of Foundations, Methodologies and Applications
VLSI Physical Design: From Graph Partitioning to Timing Closure
VLSI Physical Design: From Graph Partitioning to Timing Closure
A Formalization of the Security Features of Physical Functions
SP '11 Proceedings of the 2011 IEEE Symposium on Security and Privacy
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Physical Unclonable Functions (PUFs) extract unique chip signatures from process variations. They are used in identification, authentication, integrity verification, and anti-counterfeiting tasks. We introduce new PUF techniques that extract bits from pairwise skews between sinks of a clock network. These techniques inherit the stability of clock network, but require a return network to deliver clock pulses to a certain region, where they are compared. Our algorithms select equidistant sinks and route the return network, then derive chip-specific random bits from available data with a moderate overhead. SPICE-based evaluation of clock-PUFs using a 45nm CMOS technology validates the operability, stability, uniqueness, randomness, and their low overhead.