PathFinder: a negotiation-based performance-driven router for FPGAs
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
Global routing with crosstalk constraints
DAC '98 Proceedings of the 35th annual Design Automation Conference
Measuring routing congestion for multi-layer global routing
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
An enhanced multilevel routing system
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Wire density driven global routing for CMP variation and timing
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
IPR: an integrated placement and routing algorithm
Proceedings of the 44th annual Design Automation Conference
FastRoute 2.0: A High-quality and Efficient Global Router
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Archer: a history-driven global routing algorithm
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
High-performance routing at the nanometer scale
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
BoxRouter 2.0: architecture and implementation of a hybrid and robust global router
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
MaizeRouter: engineering an effective global router
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
A new global router for modern designs
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Robust layer assignment for via optimization in multi-layer global routing
Proceedings of the 2009 international symposium on Physical design
Proceedings of the 2009 International Conference on Computer-Aided Design
A multilevel congestion-based global router
VLSI Design
What makes a design difficult to route
Proceedings of the 19th international symposium on Physical design
Multilayer global routing with via and wire capacity considerations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Negotiation-based layer assignment for via count and via overflow minimization
Proceedings of the 16th Asia and South Pacific Design Automation Conference
An enhanced global router with consideration of general layer directives
Proceedings of the 2011 international symposium on Physical design
A SimPLR method for routability-driven placement
Proceedings of the International Conference on Computer-Aided Design
Proceedings of the International Conference on Computer-Aided Design
GLADE: a modern global router considering layer directives
Proceedings of the International Conference on Computer-Aided Design
The DAC 2012 routability-driven placement contest and benchmark suite
Proceedings of the 49th Annual Design Automation Conference
Proceedings of the International Conference on Computer-Aided Design
ICCAD-2012 CAD contest in design hierarchy aware routability-driven placement and benchmark suite
Proceedings of the International Conference on Computer-Aided Design
Delay-driven layer assignment in global routing under multi-tier interconnect structure
Proceedings of the 2013 ACM international symposium on International symposium on physical design
A routing algorithm for graphene nanoribbon circuit
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special Section on Networks on Chip: Architecture, Tools, and Methodologies
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Global routing for modern large-scale circuit designs has attracted much attention in the recent literature. Most of the state-of-the-art academic global routers just work on a simplified routing congestion model that ignores the essential via capacity for routing through multiple metal layers. Such a simplified model would easily cause fatal routability problems in subsequent detailed routing. To remedy this deficiency, we present in this paper a more effective congestion metric that considers both the in-tile nets and the residual via capacity for global routing. With this congestion metric, we develop a new global router that features two novel routing algorithms for congestion optimization, namely least-flexibility-first routing and multi-source multi-sink escaping-point routing. The least-flexibility-first routing processes the nets with the least flexibility first, facilitating a quick prediction of congestion hot spots for the subsequent nets. Enjoying lower time complexity than traditional maze and A*-search routing, in particular, the linear-time escaping-point routing guarantees to find the optimal solution and achieves the theoretical lower-bound time complexity. Experimental results show that our global router can achieve very high-quality routing solutions with more reasonable via usage, which can benefit and correctly guide subsequent detailed routing.