Principles of artificial intelligence
Principles of artificial intelligence
Introduction to algorithms
Performance driven global routing for standard cell design
Proceedings of the 1997 international symposium on Physical design
Congestion driven quadratic placement
DAC '98 Proceedings of the 35th annual Design Automation Conference
On the behavior of congestion minimization during placement
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Integrated floorplanning and interconnect planning
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Estimating routing congestion using probabilistic analysis
Proceedings of the 2001 international symposium on Physical design
Congestion estimation during top-down placement
Proceedings of the 2001 international symposium on Physical design
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Congestion aware layout driven logic synthesis
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Accurate pseudo-constructive wirelength and congestion estimation
Proceedings of the 2003 international workshop on System-level interconnect prediction
Improved global routing through congestion estimation
Proceedings of the 40th annual Design Automation Conference
Dynamic global buffer planning optimization based on detail block locating and congestion analysis
Proceedings of the 40th annual Design Automation Conference
Probabilistic congestion prediction
Proceedings of the 2004 international symposium on Physical design
A predictive distributed congestion metric and its application to technology mapping
Proceedings of the 2004 international symposium on Physical design
Routability-driven placement and white space allocation
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
BoxRouter: a new global router based on box expansion and progressive ILP
Proceedings of the 43rd annual Design Automation Conference
Via-configurable routing architectures and fast design mappability estimation for regular fabrics
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An accurate and efficient probabilistic congestion estimation model in x architecture
Proceedings of the 2007 international workshop on System level interconnect prediction
FastRoute: a step to integrate global routing into placement
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Evaluation, prediction and reduction of routing congestion
Microelectronics Journal
High-performance routing at the nanometer scale
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
BoxRouter 2.0: architecture and implementation of a hybrid and robust global router
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
The coming of age of (academic) global routing
Proceedings of the 2008 international symposium on Physical design
MaizeRouter: engineering an effective global router
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
BoxRouter 2.0: A hybrid and robust global router with layer assignment for routability
ACM Transactions on Design Automation of Electronic Systems (TODAES)
On improving optimization effectiveness in interconnect-driven physical synthesis
Proceedings of the 2009 international symposium on Physical design
A SimPLR method for routability-driven placement
Proceedings of the International Conference on Computer-Aided Design
Progress and challenges in VLSI placement research
Proceedings of the International Conference on Computer-Aided Design
Taming the complexity of coordinated place and route
Proceedings of the 50th Annual Design Automation Conference
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Fast congestion prediction is essential for congestion reduction techniques at different stages of the flow. Probabilistic congestion estimation methods model congestion after placement by considering the probability a wire will be routed over different areas of the routing region. They are popular because they are much faster than traditional global routing.In this paper, two congestion estimation tools are presented. The first one is an implementation of a probabilistic method called pce and appears to be very fast in comparison with comparable methods. The second one called FaDGloR is new and based on global routing techniques. Surprisingly, FaDGloR is about as fast as pce. The reason is that it is tuned towards congestion estimation and speed contrary to global routers that are tuned towards wire length reduction and routing as many wires as possible. Special focus is on congested areas of the chip, the areas that may prevent a design to be routable, and FaDGloR more accurately predicts these areas than pce. Both tools are tested on designs varying from impossible to route to easily routable. Previous papers focussed on accurately modeling congestion of the final, routable design. In practice, also unroutable designs need to be evaluated. The results presented in this paper indicate that global routing based methods are probably more worthwhile than probabilistic methods.