RISA: accurate and efficient placement routability modeling
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
On the behavior of congestion minimization during placement
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Modeling and minimization of routing congestion
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
The X architecture: not your father's diagonal wiring
SLIP '02 Proceedings of the 2002 international workshop on System-level interconnect prediction
Routability driven floorplanner with buffer block planning
Proceedings of the 2002 international symposium on Physical design
Accurate pseudo-constructive wirelength and congestion estimation
Proceedings of the 2003 international workshop on System-level interconnect prediction
Improved global routing through congestion estimation
Proceedings of the 40th annual Design Automation Conference
Dynamic global buffer planning optimization based on detail block locating and congestion analysis
Proceedings of the 40th annual Design Automation Conference
A New Effective Congestion Model in Floorplan Design
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Probabilistic congestion prediction
Proceedings of the 2004 international symposium on Physical design
A new paradigm for general architecture routing
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Is probabilistic congestion estimation worthwhile?
Proceedings of the 2005 international workshop on System level interconnect prediction
Multilevel full-chip routing for the X-based architecture
Proceedings of the 42nd annual Design Automation Conference
DraXRouter: global routing in X-Architecture with dynamic resource assignment
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Prediction and reduction of routing congestion
Proceedings of the 2006 international symposium on Physical design
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
Estimating routing congestion using probabilistic analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Evaluation, prediction and reduction of routing congestion
Microelectronics Journal
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Recently, the X architecture has been introduced to improve performance of the chip. Though the X architecture can reduce the wirelength significantly, routability remains a major concern in the design flow. In this paper, we formulate the congestion estimation in the X architecture based on the liquid routing technique. Based on the probabilistic analysis of the routing demand, a congestion estimation model in the X architecture is presented. An existing dynamic resource assignment (Dra) method is adopted in our model in order to obtain accurate congestion estimation. Experiments show that the congestion estimated by our model correlates well with post-routing congestion in the X architecture based on the liquid routing technique. The good accuracy and high efficiency of our model is also presented.