Manhattan or non-Manhattan?: a study of alternative VLSI routing architectures
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
Buffered Steiner trees for difficult instances
Proceedings of the 2001 international symposium on Physical design
An exact algorithm for coupling-free routing
Proceedings of the 2001 international symposium on Physical design
The X architecture: not your father's diagonal wiring
SLIP '02 Proceedings of the 2002 international workshop on System-level interconnect prediction
S-Tree: a technique for buffered routing tree synthesis
Proceedings of the 39th annual Design Automation Conference
An Introduction to VLSI Physical Design
An Introduction to VLSI Physical Design
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Constructing exact octagonal steiner minimal trees
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Congestion reduction in traditional and new routing architectures
Proceedings of the 13th ACM Great Lakes symposium on VLSI
A novel framework for multilevel routing considering routability and performance
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Improved global routing through congestion estimation
Proceedings of the 40th annual Design Automation Conference
Physical Planning Of On-Chip Interconnect Architectures
ICCD '02 Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02)
An efficient hierarchical timing-driven Steiner tree algorithm for global routing
Integration, the VLSI Journal
SSTT: efficient local search for GSI global routing
Journal of Computer Science and Technology
CNB: a critical-network-based timing optimization method for standard cell global routing
Journal of Computer Science and Technology
A new paradigm for general architecture routing
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Highly scalable algorithms for rectilinear and octilinear Steiner trees
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
The Y-architecture: yet another on-chip interconnect solution
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Creating and exploiting flexibility in rectilinear Steiner trees
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
UTACO: a unified timing and congestion optimization algorithm for standard cell global routing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Spanning graph-based nonrectilinear steiner tree algorithms
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
DraXRouter: global routing in X-Architecture with dynamic resource assignment
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
An accurate and efficient probabilistic congestion estimation model in x architecture
Proceedings of the 2007 international workshop on System level interconnect prediction
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The increment of transistors inside one chip has been following Moore's Law. To cope with dense chip design for VLSI systems, a new routing paradigm, called X-Architecture, is introduced. In this paper, we present novel resources estimation and routability models for standard cell global routing in X-Architecture. By using these models, we route the chip with a compensation-based convergent approach, called COCO, in which a random sub-tree growing (RSG) heuristic is used to construct and refine routing trees within several iterations. The router has been implemented and tested on MCNC and ISPD'98 benchmarks and some industrial circuits. The experimental results are compared with two typical existing routers (labyrinth and SSTT). It indicates that our router can reduce the total wire length and overflow more than 10% and 80% on average, respectively.